annotate src/cpu/sparc/vm/c1_FrameMap_sparc.hpp @ 0:a61af66fc99e

Initial load
author duke
date Sat, 01 Dec 2007 00:00:00 +0000
parents
children fc2c71045ada
rev   line source
duke@0 1 /*
duke@0 2 * Copyright 1999-2006 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
duke@0 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 * CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 * have any questions.
duke@0 22 *
duke@0 23 */
duke@0 24
duke@0 25 public:
duke@0 26
duke@0 27 enum {
duke@0 28 nof_reg_args = 6, // registers o0-o5 are available for parameter passing
duke@0 29 first_available_sp_in_frame = frame::memory_parameter_word_sp_offset * BytesPerWord,
duke@0 30 frame_pad_in_bytes = 0
duke@0 31 };
duke@0 32
duke@0 33 static const int pd_c_runtime_reserved_arg_size;
duke@0 34
duke@0 35 static LIR_Opr G0_opr;
duke@0 36 static LIR_Opr G1_opr;
duke@0 37 static LIR_Opr G2_opr;
duke@0 38 static LIR_Opr G3_opr;
duke@0 39 static LIR_Opr G4_opr;
duke@0 40 static LIR_Opr G5_opr;
duke@0 41 static LIR_Opr G6_opr;
duke@0 42 static LIR_Opr G7_opr;
duke@0 43 static LIR_Opr O0_opr;
duke@0 44 static LIR_Opr O1_opr;
duke@0 45 static LIR_Opr O2_opr;
duke@0 46 static LIR_Opr O3_opr;
duke@0 47 static LIR_Opr O4_opr;
duke@0 48 static LIR_Opr O5_opr;
duke@0 49 static LIR_Opr O6_opr;
duke@0 50 static LIR_Opr O7_opr;
duke@0 51 static LIR_Opr L0_opr;
duke@0 52 static LIR_Opr L1_opr;
duke@0 53 static LIR_Opr L2_opr;
duke@0 54 static LIR_Opr L3_opr;
duke@0 55 static LIR_Opr L4_opr;
duke@0 56 static LIR_Opr L5_opr;
duke@0 57 static LIR_Opr L6_opr;
duke@0 58 static LIR_Opr L7_opr;
duke@0 59 static LIR_Opr I0_opr;
duke@0 60 static LIR_Opr I1_opr;
duke@0 61 static LIR_Opr I2_opr;
duke@0 62 static LIR_Opr I3_opr;
duke@0 63 static LIR_Opr I4_opr;
duke@0 64 static LIR_Opr I5_opr;
duke@0 65 static LIR_Opr I6_opr;
duke@0 66 static LIR_Opr I7_opr;
duke@0 67
duke@0 68 static LIR_Opr SP_opr;
duke@0 69 static LIR_Opr FP_opr;
duke@0 70
duke@0 71 static LIR_Opr G0_oop_opr;
duke@0 72 static LIR_Opr G1_oop_opr;
duke@0 73 static LIR_Opr G2_oop_opr;
duke@0 74 static LIR_Opr G3_oop_opr;
duke@0 75 static LIR_Opr G4_oop_opr;
duke@0 76 static LIR_Opr G5_oop_opr;
duke@0 77 static LIR_Opr G6_oop_opr;
duke@0 78 static LIR_Opr G7_oop_opr;
duke@0 79 static LIR_Opr O0_oop_opr;
duke@0 80 static LIR_Opr O1_oop_opr;
duke@0 81 static LIR_Opr O2_oop_opr;
duke@0 82 static LIR_Opr O3_oop_opr;
duke@0 83 static LIR_Opr O4_oop_opr;
duke@0 84 static LIR_Opr O5_oop_opr;
duke@0 85 static LIR_Opr O6_oop_opr;
duke@0 86 static LIR_Opr O7_oop_opr;
duke@0 87 static LIR_Opr L0_oop_opr;
duke@0 88 static LIR_Opr L1_oop_opr;
duke@0 89 static LIR_Opr L2_oop_opr;
duke@0 90 static LIR_Opr L3_oop_opr;
duke@0 91 static LIR_Opr L4_oop_opr;
duke@0 92 static LIR_Opr L5_oop_opr;
duke@0 93 static LIR_Opr L6_oop_opr;
duke@0 94 static LIR_Opr L7_oop_opr;
duke@0 95 static LIR_Opr I0_oop_opr;
duke@0 96 static LIR_Opr I1_oop_opr;
duke@0 97 static LIR_Opr I2_oop_opr;
duke@0 98 static LIR_Opr I3_oop_opr;
duke@0 99 static LIR_Opr I4_oop_opr;
duke@0 100 static LIR_Opr I5_oop_opr;
duke@0 101 static LIR_Opr I6_oop_opr;
duke@0 102 static LIR_Opr I7_oop_opr;
duke@0 103
duke@0 104 static LIR_Opr in_long_opr;
duke@0 105 static LIR_Opr out_long_opr;
duke@0 106
duke@0 107 static LIR_Opr F0_opr;
duke@0 108 static LIR_Opr F0_double_opr;
duke@0 109
duke@0 110 static LIR_Opr Oexception_opr;
duke@0 111 static LIR_Opr Oissuing_pc_opr;
duke@0 112
duke@0 113 private:
duke@0 114 static FloatRegister _fpu_regs [nof_fpu_regs];
duke@0 115
duke@0 116 public:
duke@0 117
duke@0 118 #ifdef _LP64
duke@0 119 static LIR_Opr as_long_opr(Register r) {
duke@0 120 return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
duke@0 121 }
duke@0 122 static LIR_Opr as_pointer_opr(Register r) {
duke@0 123 return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
duke@0 124 }
duke@0 125 #else
duke@0 126 static LIR_Opr as_long_opr(Register r) {
duke@0 127 return LIR_OprFact::double_cpu(cpu_reg2rnr(r->successor()), cpu_reg2rnr(r));
duke@0 128 }
duke@0 129 static LIR_Opr as_pointer_opr(Register r) {
duke@0 130 return as_opr(r);
duke@0 131 }
duke@0 132 #endif
duke@0 133 static LIR_Opr as_float_opr(FloatRegister r) {
duke@0 134 return LIR_OprFact::single_fpu(r->encoding());
duke@0 135 }
duke@0 136 static LIR_Opr as_double_opr(FloatRegister r) {
duke@0 137 return LIR_OprFact::double_fpu(r->successor()->encoding(), r->encoding());
duke@0 138 }
duke@0 139
duke@0 140 static FloatRegister nr2floatreg (int rnr);
duke@0 141
duke@0 142 static VMReg fpu_regname (int n);
duke@0 143
duke@0 144 static bool is_caller_save_register (LIR_Opr reg);
duke@0 145 static bool is_caller_save_register (Register r);