annotate src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp @ 0:a61af66fc99e

Initial load
author duke
date Sat, 01 Dec 2007 00:00:00 +0000
parents
children d5fc211aea19
rev   line source
duke@0 1 /*
duke@0 2 * Copyright 2000-2007 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
duke@0 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 * CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 * have any questions.
duke@0 22 *
duke@0 23 */
duke@0 24
duke@0 25 # include "incls/_precompiled.incl"
duke@0 26 # include "incls/_c1_LIRAssembler_sparc.cpp.incl"
duke@0 27
duke@0 28 #define __ _masm->
duke@0 29
duke@0 30
duke@0 31 //------------------------------------------------------------
duke@0 32
duke@0 33
duke@0 34 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
duke@0 35 if (opr->is_constant()) {
duke@0 36 LIR_Const* constant = opr->as_constant_ptr();
duke@0 37 switch (constant->type()) {
duke@0 38 case T_INT: {
duke@0 39 jint value = constant->as_jint();
duke@0 40 return Assembler::is_simm13(value);
duke@0 41 }
duke@0 42
duke@0 43 default:
duke@0 44 return false;
duke@0 45 }
duke@0 46 }
duke@0 47 return false;
duke@0 48 }
duke@0 49
duke@0 50
duke@0 51 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
duke@0 52 switch (op->code()) {
duke@0 53 case lir_null_check:
duke@0 54 return true;
duke@0 55
duke@0 56
duke@0 57 case lir_add:
duke@0 58 case lir_ushr:
duke@0 59 case lir_shr:
duke@0 60 case lir_shl:
duke@0 61 // integer shifts and adds are always one instruction
duke@0 62 return op->result_opr()->is_single_cpu();
duke@0 63
duke@0 64
duke@0 65 case lir_move: {
duke@0 66 LIR_Op1* op1 = op->as_Op1();
duke@0 67 LIR_Opr src = op1->in_opr();
duke@0 68 LIR_Opr dst = op1->result_opr();
duke@0 69
duke@0 70 if (src == dst) {
duke@0 71 NEEDS_CLEANUP;
duke@0 72 // this works around a problem where moves with the same src and dst
duke@0 73 // end up in the delay slot and then the assembler swallows the mov
duke@0 74 // since it has no effect and then it complains because the delay slot
duke@0 75 // is empty. returning false stops the optimizer from putting this in
duke@0 76 // the delay slot
duke@0 77 return false;
duke@0 78 }
duke@0 79
duke@0 80 // don't put moves involving oops into the delay slot since the VerifyOops code
duke@0 81 // will make it much larger than a single instruction.
duke@0 82 if (VerifyOops) {
duke@0 83 return false;
duke@0 84 }
duke@0 85
duke@0 86 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
duke@0 87 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
duke@0 88 return false;
duke@0 89 }
duke@0 90
duke@0 91 if (dst->is_register()) {
duke@0 92 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
duke@0 93 return !PatchALot;
duke@0 94 } else if (src->is_single_stack()) {
duke@0 95 return true;
duke@0 96 }
duke@0 97 }
duke@0 98
duke@0 99 if (src->is_register()) {
duke@0 100 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
duke@0 101 return !PatchALot;
duke@0 102 } else if (dst->is_single_stack()) {
duke@0 103 return true;
duke@0 104 }
duke@0 105 }
duke@0 106
duke@0 107 if (dst->is_register() &&
duke@0 108 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
duke@0 109 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
duke@0 110 return true;
duke@0 111 }
duke@0 112
duke@0 113 return false;
duke@0 114 }
duke@0 115
duke@0 116 default:
duke@0 117 return false;
duke@0 118 }
duke@0 119 ShouldNotReachHere();
duke@0 120 }
duke@0 121
duke@0 122
duke@0 123 LIR_Opr LIR_Assembler::receiverOpr() {
duke@0 124 return FrameMap::O0_oop_opr;
duke@0 125 }
duke@0 126
duke@0 127
duke@0 128 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
duke@0 129 return FrameMap::I0_oop_opr;
duke@0 130 }
duke@0 131
duke@0 132
duke@0 133 LIR_Opr LIR_Assembler::osrBufferPointer() {
duke@0 134 return FrameMap::I0_opr;
duke@0 135 }
duke@0 136
duke@0 137
duke@0 138 int LIR_Assembler::initial_frame_size_in_bytes() {
duke@0 139 return in_bytes(frame_map()->framesize_in_bytes());
duke@0 140 }
duke@0 141
duke@0 142
duke@0 143 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
duke@0 144 // we fetch the class of the receiver (O0) and compare it with the cached class.
duke@0 145 // If they do not match we jump to slow case.
duke@0 146 int LIR_Assembler::check_icache() {
duke@0 147 int offset = __ offset();
duke@0 148 __ inline_cache_check(O0, G5_inline_cache_reg);
duke@0 149 return offset;
duke@0 150 }
duke@0 151
duke@0 152
duke@0 153 void LIR_Assembler::osr_entry() {
duke@0 154 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
duke@0 155 //
duke@0 156 // 1. Create a new compiled activation.
duke@0 157 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
duke@0 158 // at the osr_bci; it is not initialized.
duke@0 159 // 3. Jump to the continuation address in compiled code to resume execution.
duke@0 160
duke@0 161 // OSR entry point
duke@0 162 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
duke@0 163 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
duke@0 164 ValueStack* entry_state = osr_entry->end()->state();
duke@0 165 int number_of_locks = entry_state->locks_size();
duke@0 166
duke@0 167 // Create a frame for the compiled activation.
duke@0 168 __ build_frame(initial_frame_size_in_bytes());
duke@0 169
duke@0 170 // OSR buffer is
duke@0 171 //
duke@0 172 // locals[nlocals-1..0]
duke@0 173 // monitors[number_of_locks-1..0]
duke@0 174 //
duke@0 175 // locals is a direct copy of the interpreter frame so in the osr buffer
duke@0 176 // so first slot in the local array is the last local from the interpreter
duke@0 177 // and last slot is local[0] (receiver) from the interpreter
duke@0 178 //
duke@0 179 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
duke@0 180 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
duke@0 181 // in the interpreter frame (the method lock if a sync method)
duke@0 182
duke@0 183 // Initialize monitors in the compiled activation.
duke@0 184 // I0: pointer to osr buffer
duke@0 185 //
duke@0 186 // All other registers are dead at this point and the locals will be
duke@0 187 // copied into place by code emitted in the IR.
duke@0 188
duke@0 189 Register OSR_buf = osrBufferPointer()->as_register();
duke@0 190 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
duke@0 191 int monitor_offset = BytesPerWord * method()->max_locals() +
duke@0 192 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
duke@0 193 for (int i = 0; i < number_of_locks; i++) {
duke@0 194 int slot_offset = monitor_offset - ((i * BasicObjectLock::size()) * BytesPerWord);
duke@0 195 #ifdef ASSERT
duke@0 196 // verify the interpreter's monitor has a non-null object
duke@0 197 {
duke@0 198 Label L;
duke@0 199 __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::obj_offset_in_bytes()), O7);
duke@0 200 __ cmp(G0, O7);
duke@0 201 __ br(Assembler::notEqual, false, Assembler::pt, L);
duke@0 202 __ delayed()->nop();
duke@0 203 __ stop("locked object is NULL");
duke@0 204 __ bind(L);
duke@0 205 }
duke@0 206 #endif // ASSERT
duke@0 207 // Copy the lock field into the compiled activation.
duke@0 208 __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::lock_offset_in_bytes()), O7);
duke@0 209 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
duke@0 210 __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::obj_offset_in_bytes()), O7);
duke@0 211 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
duke@0 212 }
duke@0 213 }
duke@0 214 }
duke@0 215
duke@0 216
duke@0 217 // Optimized Library calls
duke@0 218 // This is the fast version of java.lang.String.compare; it has not
duke@0 219 // OSR-entry and therefore, we generate a slow version for OSR's
duke@0 220 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
duke@0 221 Register str0 = left->as_register();
duke@0 222 Register str1 = right->as_register();
duke@0 223
duke@0 224 Label Ldone;
duke@0 225
duke@0 226 Register result = dst->as_register();
duke@0 227 {
duke@0 228 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
duke@0 229 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
duke@0 230 // Also, get string0.count-string1.count in o7 and get the condition code set
duke@0 231 // Note: some instructions have been hoisted for better instruction scheduling
duke@0 232
duke@0 233 Register tmp0 = L0;
duke@0 234 Register tmp1 = L1;
duke@0 235 Register tmp2 = L2;
duke@0 236
duke@0 237 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
duke@0 238 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
duke@0 239 int count_offset = java_lang_String:: count_offset_in_bytes();
duke@0 240
duke@0 241 __ ld_ptr(Address(str0, 0, value_offset), tmp0);
duke@0 242 __ ld(Address(str0, 0, offset_offset), tmp2);
duke@0 243 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
duke@0 244 __ ld(Address(str0, 0, count_offset), str0);
duke@0 245 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
duke@0 246
duke@0 247 // str1 may be null
duke@0 248 add_debug_info_for_null_check_here(info);
duke@0 249
duke@0 250 __ ld_ptr(Address(str1, 0, value_offset), tmp1);
duke@0 251 __ add(tmp0, tmp2, tmp0);
duke@0 252
duke@0 253 __ ld(Address(str1, 0, offset_offset), tmp2);
duke@0 254 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
duke@0 255 __ ld(Address(str1, 0, count_offset), str1);
duke@0 256 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
duke@0 257 __ subcc(str0, str1, O7);
duke@0 258 __ add(tmp1, tmp2, tmp1);
duke@0 259 }
duke@0 260
duke@0 261 {
duke@0 262 // Compute the minimum of the string lengths, scale it and store it in limit
duke@0 263 Register count0 = I0;
duke@0 264 Register count1 = I1;
duke@0 265 Register limit = L3;
duke@0 266
duke@0 267 Label Lskip;
duke@0 268 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
duke@0 269 __ br(Assembler::greater, true, Assembler::pt, Lskip);
duke@0 270 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
duke@0 271 __ bind(Lskip);
duke@0 272
duke@0 273 // If either string is empty (or both of them) the result is the difference in lengths
duke@0 274 __ cmp(limit, 0);
duke@0 275 __ br(Assembler::equal, true, Assembler::pn, Ldone);
duke@0 276 __ delayed()->mov(O7, result); // result is difference in lengths
duke@0 277 }
duke@0 278
duke@0 279 {
duke@0 280 // Neither string is empty
duke@0 281 Label Lloop;
duke@0 282
duke@0 283 Register base0 = L0;
duke@0 284 Register base1 = L1;
duke@0 285 Register chr0 = I0;
duke@0 286 Register chr1 = I1;
duke@0 287 Register limit = L3;
duke@0 288
duke@0 289 // Shift base0 and base1 to the end of the arrays, negate limit
duke@0 290 __ add(base0, limit, base0);
duke@0 291 __ add(base1, limit, base1);
duke@0 292 __ neg(limit); // limit = -min{string0.count, strin1.count}
duke@0 293
duke@0 294 __ lduh(base0, limit, chr0);
duke@0 295 __ bind(Lloop);
duke@0 296 __ lduh(base1, limit, chr1);
duke@0 297 __ subcc(chr0, chr1, chr0);
duke@0 298 __ br(Assembler::notZero, false, Assembler::pn, Ldone);
duke@0 299 assert(chr0 == result, "result must be pre-placed");
duke@0 300 __ delayed()->inccc(limit, sizeof(jchar));
duke@0 301 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
duke@0 302 __ delayed()->lduh(base0, limit, chr0);
duke@0 303 }
duke@0 304
duke@0 305 // If strings are equal up to min length, return the length difference.
duke@0 306 __ mov(O7, result);
duke@0 307
duke@0 308 // Otherwise, return the difference between the first mismatched chars.
duke@0 309 __ bind(Ldone);
duke@0 310 }
duke@0 311
duke@0 312
duke@0 313 // --------------------------------------------------------------------------------------------
duke@0 314
duke@0 315 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
duke@0 316 if (!GenerateSynchronizationCode) return;
duke@0 317
duke@0 318 Register obj_reg = obj_opr->as_register();
duke@0 319 Register lock_reg = lock_opr->as_register();
duke@0 320
duke@0 321 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
duke@0 322 Register reg = mon_addr.base();
duke@0 323 int offset = mon_addr.disp();
duke@0 324 // compute pointer to BasicLock
duke@0 325 if (mon_addr.is_simm13()) {
duke@0 326 __ add(reg, offset, lock_reg);
duke@0 327 }
duke@0 328 else {
duke@0 329 __ set(offset, lock_reg);
duke@0 330 __ add(reg, lock_reg, lock_reg);
duke@0 331 }
duke@0 332 // unlock object
duke@0 333 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
duke@0 334 // _slow_case_stubs->append(slow_case);
duke@0 335 // temporary fix: must be created after exceptionhandler, therefore as call stub
duke@0 336 _slow_case_stubs->append(slow_case);
duke@0 337 if (UseFastLocking) {
duke@0 338 // try inlined fast unlocking first, revert to slow locking if it fails
duke@0 339 // note: lock_reg points to the displaced header since the displaced header offset is 0!
duke@0 340 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
duke@0 341 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
duke@0 342 } else {
duke@0 343 // always do slow unlocking
duke@0 344 // note: the slow unlocking code could be inlined here, however if we use
duke@0 345 // slow unlocking, speed doesn't matter anyway and this solution is
duke@0 346 // simpler and requires less duplicated code - additionally, the
duke@0 347 // slow unlocking code is the same in either case which simplifies
duke@0 348 // debugging
duke@0 349 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
duke@0 350 __ delayed()->nop();
duke@0 351 }
duke@0 352 // done
duke@0 353 __ bind(*slow_case->continuation());
duke@0 354 }
duke@0 355
duke@0 356
duke@0 357 void LIR_Assembler::emit_exception_handler() {
duke@0 358 // if the last instruction is a call (typically to do a throw which
duke@0 359 // is coming at the end after block reordering) the return address
duke@0 360 // must still point into the code area in order to avoid assertion
duke@0 361 // failures when searching for the corresponding bci => add a nop
duke@0 362 // (was bug 5/14/1999 - gri)
duke@0 363 __ nop();
duke@0 364
duke@0 365 // generate code for exception handler
duke@0 366 ciMethod* method = compilation()->method();
duke@0 367
duke@0 368 address handler_base = __ start_a_stub(exception_handler_size);
duke@0 369
duke@0 370 if (handler_base == NULL) {
duke@0 371 // not enough space left for the handler
duke@0 372 bailout("exception handler overflow");
duke@0 373 return;
duke@0 374 }
duke@0 375 #ifdef ASSERT
duke@0 376 int offset = code_offset();
duke@0 377 #endif // ASSERT
duke@0 378 compilation()->offsets()->set_value(CodeOffsets::Exceptions, code_offset());
duke@0 379
duke@0 380
duke@0 381 if (compilation()->has_exception_handlers() || JvmtiExport::can_post_exceptions()) {
duke@0 382 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
duke@0 383 __ delayed()->nop();
duke@0 384 }
duke@0 385
duke@0 386 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
duke@0 387 __ delayed()->nop();
duke@0 388 debug_only(__ stop("should have gone to the caller");)
duke@0 389 assert(code_offset() - offset <= exception_handler_size, "overflow");
duke@0 390
duke@0 391 __ end_a_stub();
duke@0 392 }
duke@0 393
duke@0 394 void LIR_Assembler::emit_deopt_handler() {
duke@0 395 // if the last instruction is a call (typically to do a throw which
duke@0 396 // is coming at the end after block reordering) the return address
duke@0 397 // must still point into the code area in order to avoid assertion
duke@0 398 // failures when searching for the corresponding bci => add a nop
duke@0 399 // (was bug 5/14/1999 - gri)
duke@0 400 __ nop();
duke@0 401
duke@0 402 // generate code for deopt handler
duke@0 403 ciMethod* method = compilation()->method();
duke@0 404 address handler_base = __ start_a_stub(deopt_handler_size);
duke@0 405 if (handler_base == NULL) {
duke@0 406 // not enough space left for the handler
duke@0 407 bailout("deopt handler overflow");
duke@0 408 return;
duke@0 409 }
duke@0 410 #ifdef ASSERT
duke@0 411 int offset = code_offset();
duke@0 412 #endif // ASSERT
duke@0 413 compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset());
duke@0 414
duke@0 415 Address deopt_blob(G3_scratch, SharedRuntime::deopt_blob()->unpack());
duke@0 416
duke@0 417 __ JUMP(deopt_blob, 0); // sethi;jmp
duke@0 418 __ delayed()->nop();
duke@0 419
duke@0 420 assert(code_offset() - offset <= deopt_handler_size, "overflow");
duke@0 421
duke@0 422 debug_only(__ stop("should have gone to the caller");)
duke@0 423
duke@0 424 __ end_a_stub();
duke@0 425 }
duke@0 426
duke@0 427
duke@0 428 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
duke@0 429 if (o == NULL) {
duke@0 430 __ set(NULL_WORD, reg);
duke@0 431 } else {
duke@0 432 int oop_index = __ oop_recorder()->find_index(o);
duke@0 433 RelocationHolder rspec = oop_Relocation::spec(oop_index);
duke@0 434 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
duke@0 435 }
duke@0 436 }
duke@0 437
duke@0 438
duke@0 439 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
duke@0 440 // Allocate a new index in oop table to hold the oop once it's been patched
duke@0 441 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
duke@0 442 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
duke@0 443
duke@0 444 Address addr = Address(reg, address(NULL), oop_Relocation::spec(oop_index));
duke@0 445 assert(addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
duke@0 446 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
duke@0 447 // NULL will be dynamically patched later and the patched value may be large. We must
duke@0 448 // therefore generate the sethi/add as a placeholders
duke@0 449 __ sethi(addr, true);
duke@0 450 __ add(addr, reg, 0);
duke@0 451
duke@0 452 patching_epilog(patch, lir_patch_normal, reg, info);
duke@0 453 }
duke@0 454
duke@0 455
duke@0 456 void LIR_Assembler::emit_op3(LIR_Op3* op) {
duke@0 457 Register Rdividend = op->in_opr1()->as_register();
duke@0 458 Register Rdivisor = noreg;
duke@0 459 Register Rscratch = op->in_opr3()->as_register();
duke@0 460 Register Rresult = op->result_opr()->as_register();
duke@0 461 int divisor = -1;
duke@0 462
duke@0 463 if (op->in_opr2()->is_register()) {
duke@0 464 Rdivisor = op->in_opr2()->as_register();
duke@0 465 } else {
duke@0 466 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
duke@0 467 assert(Assembler::is_simm13(divisor), "can only handle simm13");
duke@0 468 }
duke@0 469
duke@0 470 assert(Rdividend != Rscratch, "");
duke@0 471 assert(Rdivisor != Rscratch, "");
duke@0 472 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
duke@0 473
duke@0 474 if (Rdivisor == noreg && is_power_of_2(divisor)) {
duke@0 475 // convert division by a power of two into some shifts and logical operations
duke@0 476 if (op->code() == lir_idiv) {
duke@0 477 if (divisor == 2) {
duke@0 478 __ srl(Rdividend, 31, Rscratch);
duke@0 479 } else {
duke@0 480 __ sra(Rdividend, 31, Rscratch);
duke@0 481 __ and3(Rscratch, divisor - 1, Rscratch);
duke@0 482 }
duke@0 483 __ add(Rdividend, Rscratch, Rscratch);
duke@0 484 __ sra(Rscratch, log2_intptr(divisor), Rresult);
duke@0 485 return;
duke@0 486 } else {
duke@0 487 if (divisor == 2) {
duke@0 488 __ srl(Rdividend, 31, Rscratch);
duke@0 489 } else {
duke@0 490 __ sra(Rdividend, 31, Rscratch);
duke@0 491 __ and3(Rscratch, divisor - 1,Rscratch);
duke@0 492 }
duke@0 493 __ add(Rdividend, Rscratch, Rscratch);
duke@0 494 __ andn(Rscratch, divisor - 1,Rscratch);
duke@0 495 __ sub(Rdividend, Rscratch, Rresult);
duke@0 496 return;
duke@0 497 }
duke@0 498 }
duke@0 499
duke@0 500 __ sra(Rdividend, 31, Rscratch);
duke@0 501 __ wry(Rscratch);
duke@0 502 if (!VM_Version::v9_instructions_work()) {
duke@0 503 // v9 doesn't require these nops
duke@0 504 __ nop();
duke@0 505 __ nop();
duke@0 506 __ nop();
duke@0 507 __ nop();
duke@0 508 }
duke@0 509
duke@0 510 add_debug_info_for_div0_here(op->info());
duke@0 511
duke@0 512 if (Rdivisor != noreg) {
duke@0 513 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
duke@0 514 } else {
duke@0 515 assert(Assembler::is_simm13(divisor), "can only handle simm13");
duke@0 516 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
duke@0 517 }
duke@0 518
duke@0 519 Label skip;
duke@0 520 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
duke@0 521 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
duke@0 522 __ bind(skip);
duke@0 523
duke@0 524 if (op->code() == lir_irem) {
duke@0 525 if (Rdivisor != noreg) {
duke@0 526 __ smul(Rscratch, Rdivisor, Rscratch);
duke@0 527 } else {
duke@0 528 __ smul(Rscratch, divisor, Rscratch);
duke@0 529 }
duke@0 530 __ sub(Rdividend, Rscratch, Rresult);
duke@0 531 }
duke@0 532 }
duke@0 533
duke@0 534
duke@0 535 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
duke@0 536 #ifdef ASSERT
duke@0 537 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
duke@0 538 if (op->block() != NULL) _branch_target_blocks.append(op->block());
duke@0 539 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
duke@0 540 #endif
duke@0 541 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
duke@0 542
duke@0 543 if (op->cond() == lir_cond_always) {
duke@0 544 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
duke@0 545 } else if (op->code() == lir_cond_float_branch) {
duke@0 546 assert(op->ublock() != NULL, "must have unordered successor");
duke@0 547 bool is_unordered = (op->ublock() == op->block());
duke@0 548 Assembler::Condition acond;
duke@0 549 switch (op->cond()) {
duke@0 550 case lir_cond_equal: acond = Assembler::f_equal; break;
duke@0 551 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
duke@0 552 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
duke@0 553 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
duke@0 554 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
duke@0 555 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
duke@0 556 default : ShouldNotReachHere();
duke@0 557 };
duke@0 558
duke@0 559 if (!VM_Version::v9_instructions_work()) {
duke@0 560 __ nop();
duke@0 561 }
duke@0 562 __ fb( acond, false, Assembler::pn, *(op->label()));
duke@0 563 } else {
duke@0 564 assert (op->code() == lir_branch, "just checking");
duke@0 565
duke@0 566 Assembler::Condition acond;
duke@0 567 switch (op->cond()) {
duke@0 568 case lir_cond_equal: acond = Assembler::equal; break;
duke@0 569 case lir_cond_notEqual: acond = Assembler::notEqual; break;
duke@0 570 case lir_cond_less: acond = Assembler::less; break;
duke@0 571 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
duke@0 572 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
duke@0 573 case lir_cond_greater: acond = Assembler::greater; break;
duke@0 574 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
duke@0 575 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
duke@0 576 default: ShouldNotReachHere();
duke@0 577 };
duke@0 578
duke@0 579 // sparc has different condition codes for testing 32-bit
duke@0 580 // vs. 64-bit values. We could always test xcc is we could
duke@0 581 // guarantee that 32-bit loads always sign extended but that isn't
duke@0 582 // true and since sign extension isn't free, it would impose a
duke@0 583 // slight cost.
duke@0 584 #ifdef _LP64
duke@0 585 if (op->type() == T_INT) {
duke@0 586 __ br(acond, false, Assembler::pn, *(op->label()));
duke@0 587 } else
duke@0 588 #endif
duke@0 589 __ brx(acond, false, Assembler::pn, *(op->label()));
duke@0 590 }
duke@0 591 // The peephole pass fills the delay slot
duke@0 592 }
duke@0 593
duke@0 594
duke@0 595 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
duke@0 596 Bytecodes::Code code = op->bytecode();
duke@0 597 LIR_Opr dst = op->result_opr();
duke@0 598
duke@0 599 switch(code) {
duke@0 600 case Bytecodes::_i2l: {
duke@0 601 Register rlo = dst->as_register_lo();
duke@0 602 Register rhi = dst->as_register_hi();
duke@0 603 Register rval = op->in_opr()->as_register();
duke@0 604 #ifdef _LP64
duke@0 605 __ sra(rval, 0, rlo);
duke@0 606 #else
duke@0 607 __ mov(rval, rlo);
duke@0 608 __ sra(rval, BitsPerInt-1, rhi);
duke@0 609 #endif
duke@0 610 break;
duke@0 611 }
duke@0 612 case Bytecodes::_i2d:
duke@0 613 case Bytecodes::_i2f: {
duke@0 614 bool is_double = (code == Bytecodes::_i2d);
duke@0 615 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
duke@0 616 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
duke@0 617 FloatRegister rsrc = op->in_opr()->as_float_reg();
duke@0 618 if (rsrc != rdst) {
duke@0 619 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
duke@0 620 }
duke@0 621 __ fitof(w, rdst, rdst);
duke@0 622 break;
duke@0 623 }
duke@0 624 case Bytecodes::_f2i:{
duke@0 625 FloatRegister rsrc = op->in_opr()->as_float_reg();
duke@0 626 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
duke@0 627 Label L;
duke@0 628 // result must be 0 if value is NaN; test by comparing value to itself
duke@0 629 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
duke@0 630 if (!VM_Version::v9_instructions_work()) {
duke@0 631 __ nop();
duke@0 632 }
duke@0 633 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
duke@0 634 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
duke@0 635 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
duke@0 636 // move integer result from float register to int register
duke@0 637 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
duke@0 638 __ bind (L);
duke@0 639 break;
duke@0 640 }
duke@0 641 case Bytecodes::_l2i: {
duke@0 642 Register rlo = op->in_opr()->as_register_lo();
duke@0 643 Register rhi = op->in_opr()->as_register_hi();
duke@0 644 Register rdst = dst->as_register();
duke@0 645 #ifdef _LP64
duke@0 646 __ sra(rlo, 0, rdst);
duke@0 647 #else
duke@0 648 __ mov(rlo, rdst);
duke@0 649 #endif
duke@0 650 break;
duke@0 651 }
duke@0 652 case Bytecodes::_d2f:
duke@0 653 case Bytecodes::_f2d: {
duke@0 654 bool is_double = (code == Bytecodes::_f2d);
duke@0 655 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
duke@0 656 LIR_Opr val = op->in_opr();
duke@0 657 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
duke@0 658 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
duke@0 659 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
duke@0 660 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
duke@0 661 __ ftof(vw, dw, rval, rdst);
duke@0 662 break;
duke@0 663 }
duke@0 664 case Bytecodes::_i2s:
duke@0 665 case Bytecodes::_i2b: {
duke@0 666 Register rval = op->in_opr()->as_register();
duke@0 667 Register rdst = dst->as_register();
duke@0 668 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
duke@0 669 __ sll (rval, shift, rdst);
duke@0 670 __ sra (rdst, shift, rdst);
duke@0 671 break;
duke@0 672 }
duke@0 673 case Bytecodes::_i2c: {
duke@0 674 Register rval = op->in_opr()->as_register();
duke@0 675 Register rdst = dst->as_register();
duke@0 676 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
duke@0 677 __ sll (rval, shift, rdst);
duke@0 678 __ srl (rdst, shift, rdst);
duke@0 679 break;
duke@0 680 }
duke@0 681
duke@0 682 default: ShouldNotReachHere();
duke@0 683 }
duke@0 684 }
duke@0 685
duke@0 686
duke@0 687 void LIR_Assembler::align_call(LIR_Code) {
duke@0 688 // do nothing since all instructions are word aligned on sparc
duke@0 689 }
duke@0 690
duke@0 691
duke@0 692 void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) {
duke@0 693 __ call(entry, rtype);
duke@0 694 // the peephole pass fills the delay slot
duke@0 695 }
duke@0 696
duke@0 697
duke@0 698 void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) {
duke@0 699 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
duke@0 700 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
duke@0 701 __ relocate(rspec);
duke@0 702 __ call(entry, relocInfo::none);
duke@0 703 // the peephole pass fills the delay slot
duke@0 704 }
duke@0 705
duke@0 706
duke@0 707 void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) {
duke@0 708 add_debug_info_for_null_check_here(info);
duke@0 709 __ ld_ptr(Address(O0, 0, oopDesc::klass_offset_in_bytes()), G3_scratch);
duke@0 710 if (__ is_simm13(vtable_offset) ) {
duke@0 711 __ ld_ptr(G3_scratch, vtable_offset, G5_method);
duke@0 712 } else {
duke@0 713 // This will generate 2 instructions
duke@0 714 __ set(vtable_offset, G5_method);
duke@0 715 // ld_ptr, set_hi, set
duke@0 716 __ ld_ptr(G3_scratch, G5_method, G5_method);
duke@0 717 }
duke@0 718 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
duke@0 719 __ callr(G3_scratch, G0);
duke@0 720 // the peephole pass fills the delay slot
duke@0 721 }
duke@0 722
duke@0 723
duke@0 724 // load with 32-bit displacement
duke@0 725 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
duke@0 726 int load_offset = code_offset();
duke@0 727 if (Assembler::is_simm13(disp)) {
duke@0 728 if (info != NULL) add_debug_info_for_null_check_here(info);
duke@0 729 switch(ld_type) {
duke@0 730 case T_BOOLEAN: // fall through
duke@0 731 case T_BYTE : __ ldsb(s, disp, d); break;
duke@0 732 case T_CHAR : __ lduh(s, disp, d); break;
duke@0 733 case T_SHORT : __ ldsh(s, disp, d); break;
duke@0 734 case T_INT : __ ld(s, disp, d); break;
duke@0 735 case T_ADDRESS:// fall through
duke@0 736 case T_ARRAY : // fall through
duke@0 737 case T_OBJECT: __ ld_ptr(s, disp, d); break;
duke@0 738 default : ShouldNotReachHere();
duke@0 739 }
duke@0 740 } else {
duke@0 741 __ sethi(disp & ~0x3ff, O7, true);
duke@0 742 __ add(O7, disp & 0x3ff, O7);
duke@0 743 if (info != NULL) add_debug_info_for_null_check_here(info);
duke@0 744 load_offset = code_offset();
duke@0 745 switch(ld_type) {
duke@0 746 case T_BOOLEAN: // fall through
duke@0 747 case T_BYTE : __ ldsb(s, O7, d); break;
duke@0 748 case T_CHAR : __ lduh(s, O7, d); break;
duke@0 749 case T_SHORT : __ ldsh(s, O7, d); break;
duke@0 750 case T_INT : __ ld(s, O7, d); break;
duke@0 751 case T_ADDRESS:// fall through
duke@0 752 case T_ARRAY : // fall through
duke@0 753 case T_OBJECT: __ ld_ptr(s, O7, d); break;
duke@0 754 default : ShouldNotReachHere();
duke@0 755 }
duke@0 756 }
duke@0 757 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
duke@0 758 return load_offset;
duke@0 759 }
duke@0 760
duke@0 761
duke@0 762 // store with 32-bit displacement
duke@0 763 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
duke@0 764 if (Assembler::is_simm13(offset)) {
duke@0 765 if (info != NULL) add_debug_info_for_null_check_here(info);
duke@0 766 switch (type) {
duke@0 767 case T_BOOLEAN: // fall through
duke@0 768 case T_BYTE : __ stb(value, base, offset); break;
duke@0 769 case T_CHAR : __ sth(value, base, offset); break;
duke@0 770 case T_SHORT : __ sth(value, base, offset); break;
duke@0 771 case T_INT : __ stw(value, base, offset); break;
duke@0 772 case T_ADDRESS:// fall through
duke@0 773 case T_ARRAY : // fall through
duke@0 774 case T_OBJECT: __ st_ptr(value, base, offset); break;
duke@0 775 default : ShouldNotReachHere();
duke@0 776 }
duke@0 777 } else {
duke@0 778 __ sethi(offset & ~0x3ff, O7, true);
duke@0 779 __ add(O7, offset & 0x3ff, O7);
duke@0 780 if (info != NULL) add_debug_info_for_null_check_here(info);
duke@0 781 switch (type) {
duke@0 782 case T_BOOLEAN: // fall through
duke@0 783 case T_BYTE : __ stb(value, base, O7); break;
duke@0 784 case T_CHAR : __ sth(value, base, O7); break;
duke@0 785 case T_SHORT : __ sth(value, base, O7); break;
duke@0 786 case T_INT : __ stw(value, base, O7); break;
duke@0 787 case T_ADDRESS:// fall through
duke@0 788 case T_ARRAY : //fall through
duke@0 789 case T_OBJECT: __ st_ptr(value, base, O7); break;
duke@0 790 default : ShouldNotReachHere();
duke@0 791 }
duke@0 792 }
duke@0 793 // Note: Do the store before verification as the code might be patched!
duke@0 794 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
duke@0 795 }
duke@0 796
duke@0 797
duke@0 798 // load float with 32-bit displacement
duke@0 799 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
duke@0 800 FloatRegisterImpl::Width w;
duke@0 801 switch(ld_type) {
duke@0 802 case T_FLOAT : w = FloatRegisterImpl::S; break;
duke@0 803 case T_DOUBLE: w = FloatRegisterImpl::D; break;
duke@0 804 default : ShouldNotReachHere();
duke@0 805 }
duke@0 806
duke@0 807 if (Assembler::is_simm13(disp)) {
duke@0 808 if (info != NULL) add_debug_info_for_null_check_here(info);
duke@0 809 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
duke@0 810 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
duke@0 811 __ ldf(FloatRegisterImpl::S, s, disp , d);
duke@0 812 } else {
duke@0 813 __ ldf(w, s, disp, d);
duke@0 814 }
duke@0 815 } else {
duke@0 816 __ sethi(disp & ~0x3ff, O7, true);
duke@0 817 __ add(O7, disp & 0x3ff, O7);
duke@0 818 if (info != NULL) add_debug_info_for_null_check_here(info);
duke@0 819 __ ldf(w, s, O7, d);
duke@0 820 }
duke@0 821 }
duke@0 822
duke@0 823
duke@0 824 // store float with 32-bit displacement
duke@0 825 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
duke@0 826 FloatRegisterImpl::Width w;
duke@0 827 switch(type) {
duke@0 828 case T_FLOAT : w = FloatRegisterImpl::S; break;
duke@0 829 case T_DOUBLE: w = FloatRegisterImpl::D; break;
duke@0 830 default : ShouldNotReachHere();
duke@0 831 }
duke@0 832
duke@0 833 if (Assembler::is_simm13(offset)) {
duke@0 834 if (info != NULL) add_debug_info_for_null_check_here(info);
duke@0 835 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
duke@0 836 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
duke@0 837 __ stf(FloatRegisterImpl::S, value , base, offset);
duke@0 838 } else {
duke@0 839 __ stf(w, value, base, offset);
duke@0 840 }
duke@0 841 } else {
duke@0 842 __ sethi(offset & ~0x3ff, O7, true);
duke@0 843 __ add(O7, offset & 0x3ff, O7);
duke@0 844 if (info != NULL) add_debug_info_for_null_check_here(info);
duke@0 845 __ stf(w, value, O7, base);
duke@0 846 }
duke@0 847 }
duke@0 848
duke@0 849
duke@0 850 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
duke@0 851 int store_offset;
duke@0 852 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
duke@0 853 assert(!unaligned, "can't handle this");
duke@0 854 // for offsets larger than a simm13 we setup the offset in O7
duke@0 855 __ sethi(offset & ~0x3ff, O7, true);
duke@0 856 __ add(O7, offset & 0x3ff, O7);
duke@0 857 store_offset = store(from_reg, base, O7, type);
duke@0 858 } else {
duke@0 859 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
duke@0 860 store_offset = code_offset();
duke@0 861 switch (type) {
duke@0 862 case T_BOOLEAN: // fall through
duke@0 863 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
duke@0 864 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
duke@0 865 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
duke@0 866 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
duke@0 867 case T_LONG :
duke@0 868 #ifdef _LP64
duke@0 869 if (unaligned || PatchALot) {
duke@0 870 __ srax(from_reg->as_register_lo(), 32, O7);
duke@0 871 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
duke@0 872 __ stw(O7, base, offset + hi_word_offset_in_bytes);
duke@0 873 } else {
duke@0 874 __ stx(from_reg->as_register_lo(), base, offset);
duke@0 875 }
duke@0 876 #else
duke@0 877 assert(Assembler::is_simm13(offset + 4), "must be");
duke@0 878 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
duke@0 879 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
duke@0 880 #endif
duke@0 881 break;
duke@0 882 case T_ADDRESS:// fall through
duke@0 883 case T_ARRAY : // fall through
duke@0 884 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
duke@0 885 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
duke@0 886 case T_DOUBLE:
duke@0 887 {
duke@0 888 FloatRegister reg = from_reg->as_double_reg();
duke@0 889 // split unaligned stores
duke@0 890 if (unaligned || PatchALot) {
duke@0 891 assert(Assembler::is_simm13(offset + 4), "must be");
duke@0 892 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
duke@0 893 __ stf(FloatRegisterImpl::S, reg, base, offset);
duke@0 894 } else {
duke@0 895 __ stf(FloatRegisterImpl::D, reg, base, offset);
duke@0 896 }
duke@0 897 break;
duke@0 898 }
duke@0 899 default : ShouldNotReachHere();
duke@0 900 }
duke@0 901 }
duke@0 902 return store_offset;
duke@0 903 }
duke@0 904
duke@0 905
duke@0 906 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
duke@0 907 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
duke@0 908 int store_offset = code_offset();
duke@0 909 switch (type) {
duke@0 910 case T_BOOLEAN: // fall through
duke@0 911 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
duke@0 912 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
duke@0 913 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
duke@0 914 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
duke@0 915 case T_LONG :
duke@0 916 #ifdef _LP64
duke@0 917 __ stx(from_reg->as_register_lo(), base, disp);
duke@0 918 #else
duke@0 919 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
duke@0 920 __ std(from_reg->as_register_hi(), base, disp);
duke@0 921 #endif
duke@0 922 break;
duke@0 923 case T_ADDRESS:// fall through
duke@0 924 case T_ARRAY : // fall through
duke@0 925 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
duke@0 926 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
duke@0 927 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
duke@0 928 default : ShouldNotReachHere();
duke@0 929 }
duke@0 930 return store_offset;
duke@0 931 }
duke@0 932
duke@0 933
duke@0 934 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
duke@0 935 int load_offset;
duke@0 936 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
duke@0 937 assert(base != O7, "destroying register");
duke@0 938 assert(!unaligned, "can't handle this");
duke@0 939 // for offsets larger than a simm13 we setup the offset in O7
duke@0 940 __ sethi(offset & ~0x3ff, O7, true);
duke@0 941 __ add(O7, offset & 0x3ff, O7);
duke@0 942 load_offset = load(base, O7, to_reg, type);
duke@0 943 } else {
duke@0 944 load_offset = code_offset();
duke@0 945 switch(type) {
duke@0 946 case T_BOOLEAN: // fall through
duke@0 947 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
duke@0 948 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
duke@0 949 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
duke@0 950 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
duke@0 951 case T_LONG :
duke@0 952 if (!unaligned) {
duke@0 953 #ifdef _LP64
duke@0 954 __ ldx(base, offset, to_reg->as_register_lo());
duke@0 955 #else
duke@0 956 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
duke@0 957 "must be sequential");
duke@0 958 __ ldd(base, offset, to_reg->as_register_hi());
duke@0 959 #endif
duke@0 960 } else {
duke@0 961 #ifdef _LP64
duke@0 962 assert(base != to_reg->as_register_lo(), "can't handle this");
duke@0 963 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
duke@0 964 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
duke@0 965 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
duke@0 966 #else
duke@0 967 if (base == to_reg->as_register_lo()) {
duke@0 968 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
duke@0 969 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
duke@0 970 } else {
duke@0 971 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
duke@0 972 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
duke@0 973 }
duke@0 974 #endif
duke@0 975 }
duke@0 976 break;
duke@0 977 case T_ADDRESS:// fall through
duke@0 978 case T_ARRAY : // fall through
duke@0 979 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
duke@0 980 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
duke@0 981 case T_DOUBLE:
duke@0 982 {
duke@0 983 FloatRegister reg = to_reg->as_double_reg();
duke@0 984 // split unaligned loads
duke@0 985 if (unaligned || PatchALot) {
duke@0 986 __ ldf(FloatRegisterImpl::S, base, offset + BytesPerWord, reg->successor());
duke@0 987 __ ldf(FloatRegisterImpl::S, base, offset, reg);
duke@0 988 } else {
duke@0 989 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
duke@0 990 }
duke@0 991 break;
duke@0 992 }
duke@0 993 default : ShouldNotReachHere();
duke@0 994 }
duke@0 995 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
duke@0 996 }
duke@0 997 return load_offset;
duke@0 998 }
duke@0 999
duke@0 1000
duke@0 1001 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
duke@0 1002 int load_offset = code_offset();
duke@0 1003 switch(type) {
duke@0 1004 case T_BOOLEAN: // fall through
duke@0 1005 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
duke@0 1006 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
duke@0 1007 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
duke@0 1008 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
duke@0 1009 case T_ADDRESS:// fall through
duke@0 1010 case T_ARRAY : // fall through
duke@0 1011 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
duke@0 1012 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
duke@0 1013 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
duke@0 1014 case T_LONG :
duke@0 1015 #ifdef _LP64
duke@0 1016 __ ldx(base, disp, to_reg->as_register_lo());
duke@0 1017 #else
duke@0 1018 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
duke@0 1019 "must be sequential");
duke@0 1020 __ ldd(base, disp, to_reg->as_register_hi());
duke@0 1021 #endif
duke@0 1022 break;
duke@0 1023 default : ShouldNotReachHere();
duke@0 1024 }
duke@0 1025 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
duke@0 1026 return load_offset;
duke@0 1027 }
duke@0 1028
duke@0 1029
duke@0 1030 // load/store with an Address
duke@0 1031 void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) {
duke@0 1032 load(a.base(), a.disp() + offset, d, ld_type, info);
duke@0 1033 }
duke@0 1034
duke@0 1035
duke@0 1036 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
duke@0 1037 store(value, dest.base(), dest.disp() + offset, type, info);
duke@0 1038 }
duke@0 1039
duke@0 1040
duke@0 1041 // loadf/storef with an Address
duke@0 1042 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
duke@0 1043 load(a.base(), a.disp() + offset, d, ld_type, info);
duke@0 1044 }
duke@0 1045
duke@0 1046
duke@0 1047 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
duke@0 1048 store(value, dest.base(), dest.disp() + offset, type, info);
duke@0 1049 }
duke@0 1050
duke@0 1051
duke@0 1052 // load/store with an Address
duke@0 1053 void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) {
duke@0 1054 load(as_Address(a), d, ld_type, info);
duke@0 1055 }
duke@0 1056
duke@0 1057
duke@0 1058 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
duke@0 1059 store(value, as_Address(dest), type, info);
duke@0 1060 }
duke@0 1061
duke@0 1062
duke@0 1063 // loadf/storef with an Address
duke@0 1064 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
duke@0 1065 load(as_Address(a), d, ld_type, info);
duke@0 1066 }
duke@0 1067
duke@0 1068
duke@0 1069 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
duke@0 1070 store(value, as_Address(dest), type, info);
duke@0 1071 }
duke@0 1072
duke@0 1073
duke@0 1074 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
duke@0 1075 LIR_Const* c = src->as_constant_ptr();
duke@0 1076 switch (c->type()) {
duke@0 1077 case T_INT:
duke@0 1078 case T_FLOAT: {
duke@0 1079 Register src_reg = O7;
duke@0 1080 int value = c->as_jint_bits();
duke@0 1081 if (value == 0) {
duke@0 1082 src_reg = G0;
duke@0 1083 } else {
duke@0 1084 __ set(value, O7);
duke@0 1085 }
duke@0 1086 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
duke@0 1087 __ stw(src_reg, addr.base(), addr.disp());
duke@0 1088 break;
duke@0 1089 }
duke@0 1090 case T_OBJECT: {
duke@0 1091 Register src_reg = O7;
duke@0 1092 jobject2reg(c->as_jobject(), src_reg);
duke@0 1093 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
duke@0 1094 __ st_ptr(src_reg, addr.base(), addr.disp());
duke@0 1095 break;
duke@0 1096 }
duke@0 1097 case T_LONG:
duke@0 1098 case T_DOUBLE: {
duke@0 1099 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
duke@0 1100
duke@0 1101 Register tmp = O7;
duke@0 1102 int value_lo = c->as_jint_lo_bits();
duke@0 1103 if (value_lo == 0) {
duke@0 1104 tmp = G0;
duke@0 1105 } else {
duke@0 1106 __ set(value_lo, O7);
duke@0 1107 }
duke@0 1108 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
duke@0 1109 int value_hi = c->as_jint_hi_bits();
duke@0 1110 if (value_hi == 0) {
duke@0 1111 tmp = G0;
duke@0 1112 } else {
duke@0 1113 __ set(value_hi, O7);
duke@0 1114 }
duke@0 1115 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
duke@0 1116 break;
duke@0 1117 }
duke@0 1118 default:
duke@0 1119 Unimplemented();
duke@0 1120 }
duke@0 1121 }
duke@0 1122
duke@0 1123
duke@0 1124 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
duke@0 1125 LIR_Const* c = src->as_constant_ptr();
duke@0 1126 LIR_Address* addr = dest->as_address_ptr();
duke@0 1127 Register base = addr->base()->as_pointer_register();
duke@0 1128
duke@0 1129 if (info != NULL) {
duke@0 1130 add_debug_info_for_null_check_here(info);
duke@0 1131 }
duke@0 1132 switch (c->type()) {
duke@0 1133 case T_INT:
duke@0 1134 case T_FLOAT: {
duke@0 1135 LIR_Opr tmp = FrameMap::O7_opr;
duke@0 1136 int value = c->as_jint_bits();
duke@0 1137 if (value == 0) {
duke@0 1138 tmp = FrameMap::G0_opr;
duke@0 1139 } else if (Assembler::is_simm13(value)) {
duke@0 1140 __ set(value, O7);
duke@0 1141 }
duke@0 1142 if (addr->index()->is_valid()) {
duke@0 1143 assert(addr->disp() == 0, "must be zero");
duke@0 1144 store(tmp, base, addr->index()->as_pointer_register(), type);
duke@0 1145 } else {
duke@0 1146 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
duke@0 1147 store(tmp, base, addr->disp(), type);
duke@0 1148 }
duke@0 1149 break;
duke@0 1150 }
duke@0 1151 case T_LONG:
duke@0 1152 case T_DOUBLE: {
duke@0 1153 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
duke@0 1154 assert(Assembler::is_simm13(addr->disp()) &&
duke@0 1155 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
duke@0 1156
duke@0 1157 Register tmp = O7;
duke@0 1158 int value_lo = c->as_jint_lo_bits();
duke@0 1159 if (value_lo == 0) {
duke@0 1160 tmp = G0;
duke@0 1161 } else {
duke@0 1162 __ set(value_lo, O7);
duke@0 1163 }
duke@0 1164 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
duke@0 1165 int value_hi = c->as_jint_hi_bits();
duke@0 1166 if (value_hi == 0) {
duke@0 1167 tmp = G0;
duke@0 1168 } else {
duke@0 1169 __ set(value_hi, O7);
duke@0 1170 }
duke@0 1171 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
duke@0 1172 break;
duke@0 1173 }
duke@0 1174 case T_OBJECT: {
duke@0 1175 jobject obj = c->as_jobject();
duke@0 1176 LIR_Opr tmp;
duke@0 1177 if (obj == NULL) {
duke@0 1178 tmp = FrameMap::G0_opr;
duke@0 1179 } else {
duke@0 1180 tmp = FrameMap::O7_opr;
duke@0 1181 jobject2reg(c->as_jobject(), O7);
duke@0 1182 }
duke@0 1183 // handle either reg+reg or reg+disp address
duke@0 1184 if (addr->index()->is_valid()) {
duke@0 1185 assert(addr->disp() == 0, "must be zero");
duke@0 1186 store(tmp, base, addr->index()->as_pointer_register(), type);
duke@0 1187 } else {
duke@0 1188 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
duke@0 1189 store(tmp, base, addr->disp(), type);
duke@0 1190 }
duke@0 1191
duke@0 1192 break;
duke@0 1193 }
duke@0 1194 default:
duke@0 1195 Unimplemented();
duke@0 1196 }
duke@0 1197 }
duke@0 1198
duke@0 1199
duke@0 1200 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
duke@0 1201 LIR_Const* c = src->as_constant_ptr();
duke@0 1202 LIR_Opr to_reg = dest;
duke@0 1203
duke@0 1204 switch (c->type()) {
duke@0 1205 case T_INT:
duke@0 1206 {
duke@0 1207 jint con = c->as_jint();
duke@0 1208 if (to_reg->is_single_cpu()) {
duke@0 1209 assert(patch_code == lir_patch_none, "no patching handled here");
duke@0 1210 __ set(con, to_reg->as_register());
duke@0 1211 } else {
duke@0 1212 ShouldNotReachHere();
duke@0 1213 assert(to_reg->is_single_fpu(), "wrong register kind");
duke@0 1214
duke@0 1215 __ set(con, O7);
duke@0 1216 Address temp_slot(SP, 0, (frame::register_save_words * wordSize) + STACK_BIAS);
duke@0 1217 __ st(O7, temp_slot);
duke@0 1218 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
duke@0 1219 }
duke@0 1220 }
duke@0 1221 break;
duke@0 1222
duke@0 1223 case T_LONG:
duke@0 1224 {
duke@0 1225 jlong con = c->as_jlong();
duke@0 1226
duke@0 1227 if (to_reg->is_double_cpu()) {
duke@0 1228 #ifdef _LP64
duke@0 1229 __ set(con, to_reg->as_register_lo());
duke@0 1230 #else
duke@0 1231 __ set(low(con), to_reg->as_register_lo());
duke@0 1232 __ set(high(con), to_reg->as_register_hi());
duke@0 1233 #endif
duke@0 1234 #ifdef _LP64
duke@0 1235 } else if (to_reg->is_single_cpu()) {
duke@0 1236 __ set(con, to_reg->as_register());
duke@0 1237 #endif
duke@0 1238 } else {
duke@0 1239 ShouldNotReachHere();
duke@0 1240 assert(to_reg->is_double_fpu(), "wrong register kind");
duke@0 1241 Address temp_slot_lo(SP, 0, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
duke@0 1242 Address temp_slot_hi(SP, 0, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
duke@0 1243 __ set(low(con), O7);
duke@0 1244 __ st(O7, temp_slot_lo);
duke@0 1245 __ set(high(con), O7);
duke@0 1246 __ st(O7, temp_slot_hi);
duke@0 1247 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
duke@0 1248 }
duke@0 1249 }
duke@0 1250 break;
duke@0 1251
duke@0 1252 case T_OBJECT:
duke@0 1253 {
duke@0 1254 if (patch_code == lir_patch_none) {
duke@0 1255 jobject2reg(c->as_jobject(), to_reg->as_register());
duke@0 1256 } else {
duke@0 1257 jobject2reg_with_patching(to_reg->as_register(), info);
duke@0 1258 }
duke@0 1259 }
duke@0 1260 break;
duke@0 1261
duke@0 1262 case T_FLOAT:
duke@0 1263 {
duke@0 1264 address const_addr = __ float_constant(c->as_jfloat());
duke@0 1265 if (const_addr == NULL) {
duke@0 1266 bailout("const section overflow");
duke@0 1267 break;
duke@0 1268 }
duke@0 1269 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
duke@0 1270 if (to_reg->is_single_fpu()) {
duke@0 1271 __ sethi( (intx)const_addr & ~0x3ff, O7, true, rspec);
duke@0 1272 __ relocate(rspec);
duke@0 1273
duke@0 1274 int offset = (intx)const_addr & 0x3ff;
duke@0 1275 __ ldf (FloatRegisterImpl::S, O7, offset, to_reg->as_float_reg());
duke@0 1276
duke@0 1277 } else {
duke@0 1278 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
duke@0 1279
duke@0 1280 __ set((intx)const_addr, O7, rspec);
duke@0 1281 load(O7, 0, to_reg->as_register(), T_INT);
duke@0 1282 }
duke@0 1283 }
duke@0 1284 break;
duke@0 1285
duke@0 1286 case T_DOUBLE:
duke@0 1287 {
duke@0 1288 address const_addr = __ double_constant(c->as_jdouble());
duke@0 1289 if (const_addr == NULL) {
duke@0 1290 bailout("const section overflow");
duke@0 1291 break;
duke@0 1292 }
duke@0 1293 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
duke@0 1294
duke@0 1295 if (to_reg->is_double_fpu()) {
duke@0 1296 __ sethi( (intx)const_addr & ~0x3ff, O7, true, rspec);
duke@0 1297 int offset = (intx)const_addr & 0x3ff;
duke@0 1298 __ relocate(rspec);
duke@0 1299 __ ldf (FloatRegisterImpl::D, O7, offset, to_reg->as_double_reg());
duke@0 1300 } else {
duke@0 1301 assert(to_reg->is_double_cpu(), "Must be a long register.");
duke@0 1302 #ifdef _LP64
duke@0 1303 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
duke@0 1304 #else
duke@0 1305 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
duke@0 1306 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
duke@0 1307 #endif
duke@0 1308 }
duke@0 1309
duke@0 1310 }
duke@0 1311 break;
duke@0 1312
duke@0 1313 default:
duke@0 1314 ShouldNotReachHere();
duke@0 1315 }
duke@0 1316 }
duke@0 1317
duke@0 1318 Address LIR_Assembler::as_Address(LIR_Address* addr) {
duke@0 1319 Register reg = addr->base()->as_register();
duke@0 1320 return Address(reg, 0, addr->disp());
duke@0 1321 }
duke@0 1322
duke@0 1323
duke@0 1324 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
duke@0 1325 switch (type) {
duke@0 1326 case T_INT:
duke@0 1327 case T_FLOAT: {
duke@0 1328 Register tmp = O7;
duke@0 1329 Address from = frame_map()->address_for_slot(src->single_stack_ix());
duke@0 1330 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
duke@0 1331 __ lduw(from.base(), from.disp(), tmp);
duke@0 1332 __ stw(tmp, to.base(), to.disp());
duke@0 1333 break;
duke@0 1334 }
duke@0 1335 case T_OBJECT: {
duke@0 1336 Register tmp = O7;
duke@0 1337 Address from = frame_map()->address_for_slot(src->single_stack_ix());
duke@0 1338 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
duke@0 1339 __ ld_ptr(from.base(), from.disp(), tmp);
duke@0 1340 __ st_ptr(tmp, to.base(), to.disp());
duke@0 1341 break;
duke@0 1342 }
duke@0 1343 case T_LONG:
duke@0 1344 case T_DOUBLE: {
duke@0 1345 Register tmp = O7;
duke@0 1346 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
duke@0 1347 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
duke@0 1348 __ lduw(from.base(), from.disp(), tmp);
duke@0 1349 __ stw(tmp, to.base(), to.disp());
duke@0 1350 __ lduw(from.base(), from.disp() + 4, tmp);
duke@0 1351 __ stw(tmp, to.base(), to.disp() + 4);
duke@0 1352 break;
duke@0 1353 }
duke@0 1354
duke@0 1355 default:
duke@0 1356 ShouldNotReachHere();
duke@0 1357 }
duke@0 1358 }
duke@0 1359
duke@0 1360
duke@0 1361 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
duke@0 1362 Address base = as_Address(addr);
duke@0 1363 return Address(base.base(), 0, base.disp() + hi_word_offset_in_bytes);
duke@0 1364 }
duke@0 1365
duke@0 1366
duke@0 1367 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
duke@0 1368 Address base = as_Address(addr);
duke@0 1369 return Address(base.base(), 0, base.disp() + lo_word_offset_in_bytes);
duke@0 1370 }
duke@0 1371
duke@0 1372
duke@0 1373 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
duke@0 1374 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
duke@0 1375
duke@0 1376 LIR_Address* addr = src_opr->as_address_ptr();
duke@0 1377 LIR_Opr to_reg = dest;
duke@0 1378
duke@0 1379 Register src = addr->base()->as_pointer_register();
duke@0 1380 Register disp_reg = noreg;
duke@0 1381 int disp_value = addr->disp();
duke@0 1382 bool needs_patching = (patch_code != lir_patch_none);
duke@0 1383
duke@0 1384 if (addr->base()->type() == T_OBJECT) {
duke@0 1385 __ verify_oop(src);
duke@0 1386 }
duke@0 1387
duke@0 1388 PatchingStub* patch = NULL;
duke@0 1389 if (needs_patching) {
duke@0 1390 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
duke@0 1391 assert(!to_reg->is_double_cpu() ||
duke@0 1392 patch_code == lir_patch_none ||
duke@0 1393 patch_code == lir_patch_normal, "patching doesn't match register");
duke@0 1394 }
duke@0 1395
duke@0 1396 if (addr->index()->is_illegal()) {
duke@0 1397 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
duke@0 1398 if (needs_patching) {
duke@0 1399 __ sethi(0, O7, true);
duke@0 1400 __ add(O7, 0, O7);
duke@0 1401 } else {
duke@0 1402 __ set(disp_value, O7);
duke@0 1403 }
duke@0 1404 disp_reg = O7;
duke@0 1405 }
duke@0 1406 } else if (unaligned || PatchALot) {
duke@0 1407 __ add(src, addr->index()->as_register(), O7);
duke@0 1408 src = O7;
duke@0 1409 } else {
duke@0 1410 disp_reg = addr->index()->as_pointer_register();
duke@0 1411 assert(disp_value == 0, "can't handle 3 operand addresses");
duke@0 1412 }
duke@0 1413
duke@0 1414 // remember the offset of the load. The patching_epilog must be done
duke@0 1415 // before the call to add_debug_info, otherwise the PcDescs don't get
duke@0 1416 // entered in increasing order.
duke@0 1417 int offset = code_offset();
duke@0 1418
duke@0 1419 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
duke@0 1420 if (disp_reg == noreg) {
duke@0 1421 offset = load(src, disp_value, to_reg, type, unaligned);
duke@0 1422 } else {
duke@0 1423 assert(!unaligned, "can't handle this");
duke@0 1424 offset = load(src, disp_reg, to_reg, type);
duke@0 1425 }
duke@0 1426
duke@0 1427 if (patch != NULL) {
duke@0 1428 patching_epilog(patch, patch_code, src, info);
duke@0 1429 }
duke@0 1430
duke@0 1431 if (info != NULL) add_debug_info_for_null_check(offset, info);
duke@0 1432 }
duke@0 1433
duke@0 1434
duke@0 1435 void LIR_Assembler::prefetchr(LIR_Opr src) {
duke@0 1436 LIR_Address* addr = src->as_address_ptr();
duke@0 1437 Address from_addr = as_Address(addr);
duke@0 1438
duke@0 1439 if (VM_Version::has_v9()) {
duke@0 1440 __ prefetch(from_addr, Assembler::severalReads);
duke@0 1441 }
duke@0 1442 }
duke@0 1443
duke@0 1444
duke@0 1445 void LIR_Assembler::prefetchw(LIR_Opr src) {
duke@0 1446 LIR_Address* addr = src->as_address_ptr();
duke@0 1447 Address from_addr = as_Address(addr);
duke@0 1448
duke@0 1449 if (VM_Version::has_v9()) {
duke@0 1450 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
duke@0 1451 }
duke@0 1452 }
duke@0 1453
duke@0 1454
duke@0 1455 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
duke@0 1456 Address addr;
duke@0 1457 if (src->is_single_word()) {
duke@0 1458 addr = frame_map()->address_for_slot(src->single_stack_ix());
duke@0 1459 } else if (src->is_double_word()) {
duke@0 1460 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
duke@0 1461 }
duke@0 1462
duke@0 1463 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
duke@0 1464 load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
duke@0 1465 }
duke@0 1466
duke@0 1467
duke@0 1468 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
duke@0 1469 Address addr;
duke@0 1470 if (dest->is_single_word()) {
duke@0 1471 addr = frame_map()->address_for_slot(dest->single_stack_ix());
duke@0 1472 } else if (dest->is_double_word()) {
duke@0 1473 addr = frame_map()->address_for_slot(dest->double_stack_ix());
duke@0 1474 }
duke@0 1475 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
duke@0 1476 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
duke@0 1477 }
duke@0 1478
duke@0 1479
duke@0 1480 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
duke@0 1481 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
duke@0 1482 if (from_reg->is_double_fpu()) {
duke@0 1483 // double to double moves
duke@0 1484 assert(to_reg->is_double_fpu(), "should match");
duke@0 1485 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
duke@0 1486 } else {
duke@0 1487 // float to float moves
duke@0 1488 assert(to_reg->is_single_fpu(), "should match");
duke@0 1489 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
duke@0 1490 }
duke@0 1491 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
duke@0 1492 if (from_reg->is_double_cpu()) {
duke@0 1493 #ifdef _LP64
duke@0 1494 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
duke@0 1495 #else
duke@0 1496 assert(to_reg->is_double_cpu() &&
duke@0 1497 from_reg->as_register_hi() != to_reg->as_register_lo() &&
duke@0 1498 from_reg->as_register_lo() != to_reg->as_register_hi(),
duke@0 1499 "should both be long and not overlap");
duke@0 1500 // long to long moves
duke@0 1501 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
duke@0 1502 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
duke@0 1503 #endif
duke@0 1504 #ifdef _LP64
duke@0 1505 } else if (to_reg->is_double_cpu()) {
duke@0 1506 // int to int moves
duke@0 1507 __ mov(from_reg->as_register(), to_reg->as_register_lo());
duke@0 1508 #endif
duke@0 1509 } else {
duke@0 1510 // int to int moves
duke@0 1511 __ mov(from_reg->as_register(), to_reg->as_register());
duke@0 1512 }
duke@0 1513 } else {
duke@0 1514 ShouldNotReachHere();
duke@0 1515 }
duke@0 1516 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
duke@0 1517 __ verify_oop(to_reg->as_register());
duke@0 1518 }
duke@0 1519 }
duke@0 1520
duke@0 1521
duke@0 1522 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
duke@0 1523 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
duke@0 1524 bool unaligned) {
duke@0 1525 LIR_Address* addr = dest->as_address_ptr();
duke@0 1526
duke@0 1527 Register src = addr->base()->as_pointer_register();
duke@0 1528 Register disp_reg = noreg;
duke@0 1529 int disp_value = addr->disp();
duke@0 1530 bool needs_patching = (patch_code != lir_patch_none);
duke@0 1531
duke@0 1532 if (addr->base()->is_oop_register()) {
duke@0 1533 __ verify_oop(src);
duke@0 1534 }
duke@0 1535
duke@0 1536 PatchingStub* patch = NULL;
duke@0 1537 if (needs_patching) {
duke@0 1538 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
duke@0 1539 assert(!from_reg->is_double_cpu() ||
duke@0 1540 patch_code == lir_patch_none ||
duke@0 1541 patch_code == lir_patch_normal, "patching doesn't match register");
duke@0 1542 }
duke@0 1543
duke@0 1544 if (addr->index()->is_illegal()) {
duke@0 1545 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
duke@0 1546 if (needs_patching) {
duke@0 1547 __ sethi(0, O7, true);
duke@0 1548 __ add(O7, 0, O7);
duke@0 1549 } else {
duke@0 1550 __ set(disp_value, O7);
duke@0 1551 }
duke@0 1552 disp_reg = O7;
duke@0 1553 }
duke@0 1554 } else if (unaligned || PatchALot) {
duke@0 1555 __ add(src, addr->index()->as_register(), O7);
duke@0 1556 src = O7;
duke@0 1557 } else {
duke@0 1558 disp_reg = addr->index()->as_pointer_register();
duke@0 1559 assert(disp_value == 0, "can't handle 3 operand addresses");
duke@0 1560 }
duke@0 1561
duke@0 1562 // remember the offset of the store. The patching_epilog must be done
duke@0 1563 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
duke@0 1564 // entered in increasing order.
duke@0 1565 int offset;
duke@0 1566
duke@0 1567 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
duke@0 1568 if (disp_reg == noreg) {
duke@0 1569 offset = store(from_reg, src, disp_value, type, unaligned);
duke@0 1570 } else {
duke@0 1571 assert(!unaligned, "can't handle this");
duke@0 1572 offset = store(from_reg, src, disp_reg, type);
duke@0 1573 }
duke@0 1574
duke@0 1575 if (patch != NULL) {
duke@0 1576 patching_epilog(patch, patch_code, src, info);
duke@0 1577 }
duke@0 1578
duke@0 1579 if (info != NULL) add_debug_info_for_null_check(offset, info);
duke@0 1580 }
duke@0 1581
duke@0 1582
duke@0 1583 void LIR_Assembler::return_op(LIR_Opr result) {
duke@0 1584 // the poll may need a register so just pick one that isn't the return register
duke@0 1585 #ifdef TIERED
duke@0 1586 if (result->type_field() == LIR_OprDesc::long_type) {
duke@0 1587 // Must move the result to G1
duke@0 1588 // Must leave proper result in O0,O1 and G1 (TIERED only)
duke@0 1589 __ sllx(I0, 32, G1); // Shift bits into high G1
duke@0 1590 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
duke@0 1591 __ or3 (I1, G1, G1); // OR 64 bits into G1
duke@0 1592 }
duke@0 1593 #endif // TIERED
duke@0 1594 __ set((intptr_t)os::get_polling_page(), L0);
duke@0 1595 __ relocate(relocInfo::poll_return_type);
duke@0 1596 __ ld_ptr(L0, 0, G0);
duke@0 1597 __ ret();
duke@0 1598 __ delayed()->restore();
duke@0 1599 }
duke@0 1600
duke@0 1601
duke@0 1602 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
duke@0 1603 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
duke@0 1604 if (info != NULL) {
duke@0 1605 add_debug_info_for_branch(info);
duke@0 1606 } else {
duke@0 1607 __ relocate(relocInfo::poll_type);
duke@0 1608 }
duke@0 1609
duke@0 1610 int offset = __ offset();
duke@0 1611 __ ld_ptr(tmp->as_register(), 0, G0);
duke@0 1612
duke@0 1613 return offset;
duke@0 1614 }
duke@0 1615
duke@0 1616
duke@0 1617 void LIR_Assembler::emit_static_call_stub() {
duke@0 1618 address call_pc = __ pc();
duke@0 1619 address stub = __ start_a_stub(call_stub_size);
duke@0 1620 if (stub == NULL) {
duke@0 1621 bailout("static call stub overflow");
duke@0 1622 return;
duke@0 1623 }
duke@0 1624
duke@0 1625 int start = __ offset();
duke@0 1626 __ relocate(static_stub_Relocation::spec(call_pc));
duke@0 1627
duke@0 1628 __ set_oop(NULL, G5);
duke@0 1629 // must be set to -1 at code generation time
duke@0 1630 Address a(G3, (address)-1);
duke@0 1631 __ jump_to(a, 0);
duke@0 1632 __ delayed()->nop();
duke@0 1633
duke@0 1634 assert(__ offset() - start <= call_stub_size, "stub too big");
duke@0 1635 __ end_a_stub();
duke@0 1636 }
duke@0 1637
duke@0 1638
duke@0 1639 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
duke@0 1640 if (opr1->is_single_fpu()) {
duke@0 1641 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
duke@0 1642 } else if (opr1->is_double_fpu()) {
duke@0 1643 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
duke@0 1644 } else if (opr1->is_single_cpu()) {
duke@0 1645 if (opr2->is_constant()) {
duke@0 1646 switch (opr2->as_constant_ptr()->type()) {
duke@0 1647 case T_INT:
duke@0 1648 { jint con = opr2->as_constant_ptr()->as_jint();
duke@0 1649 if (Assembler::is_simm13(con)) {
duke@0 1650 __ cmp(opr1->as_register(), con);
duke@0 1651 } else {
duke@0 1652 __ set(con, O7);
duke@0 1653 __ cmp(opr1->as_register(), O7);
duke@0 1654 }
duke@0 1655 }
duke@0 1656 break;
duke@0 1657
duke@0 1658 case T_OBJECT:
duke@0 1659 // there are only equal/notequal comparisions on objects
duke@0 1660 { jobject con = opr2->as_constant_ptr()->as_jobject();
duke@0 1661 if (con == NULL) {
duke@0 1662 __ cmp(opr1->as_register(), 0);
duke@0 1663 } else {
duke@0 1664 jobject2reg(con, O7);
duke@0 1665 __ cmp(opr1->as_register(), O7);
duke@0 1666 }
duke@0 1667 }
duke@0 1668 break;
duke@0 1669
duke@0 1670 default:
duke@0 1671 ShouldNotReachHere();
duke@0 1672 break;
duke@0 1673 }
duke@0 1674 } else {
duke@0 1675 if (opr2->is_address()) {
duke@0 1676 LIR_Address * addr = opr2->as_address_ptr();
duke@0 1677 BasicType type = addr->type();
duke@0 1678 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
duke@0 1679 else __ ld(as_Address(addr), O7);
duke@0 1680 __ cmp(opr1->as_register(), O7);
duke@0 1681 } else {
duke@0 1682 __ cmp(opr1->as_register(), opr2->as_register());
duke@0 1683 }
duke@0 1684 }
duke@0 1685 } else if (opr1->is_double_cpu()) {
duke@0 1686 Register xlo = opr1->as_register_lo();
duke@0 1687 Register xhi = opr1->as_register_hi();
duke@0 1688 if (opr2->is_constant() && opr2->as_jlong() == 0) {
duke@0 1689 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
duke@0 1690 #ifdef _LP64
duke@0 1691 __ orcc(xhi, G0, G0);
duke@0 1692 #else
duke@0 1693 __ orcc(xhi, xlo, G0);
duke@0 1694 #endif
duke@0 1695 } else if (opr2->is_register()) {
duke@0 1696 Register ylo = opr2->as_register_lo();
duke@0 1697 Register yhi = opr2->as_register_hi();
duke@0 1698 #ifdef _LP64
duke@0 1699 __ cmp(xlo, ylo);
duke@0 1700 #else
duke@0 1701 __ subcc(xlo, ylo, xlo);
duke@0 1702 __ subccc(xhi, yhi, xhi);
duke@0 1703 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
duke@0 1704 __ orcc(xhi, xlo, G0);
duke@0 1705 }
duke@0 1706 #endif
duke@0 1707 } else {
duke@0 1708 ShouldNotReachHere();
duke@0 1709 }
duke@0 1710 } else if (opr1->is_address()) {
duke@0 1711 LIR_Address * addr = opr1->as_address_ptr();
duke@0 1712 BasicType type = addr->type();
duke@0 1713 assert (opr2->is_constant(), "Checking");
duke@0 1714 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
duke@0 1715 else __ ld(as_Address(addr), O7);
duke@0 1716 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
duke@0 1717 } else {
duke@0 1718 ShouldNotReachHere();
duke@0 1719 }
duke@0 1720 }
duke@0 1721
duke@0 1722
duke@0 1723 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
duke@0 1724 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
duke@0 1725 bool is_unordered_less = (code == lir_ucmp_fd2i);
duke@0 1726 if (left->is_single_fpu()) {
duke@0 1727 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
duke@0 1728 } else if (left->is_double_fpu()) {
duke@0 1729 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
duke@0 1730 } else {
duke@0 1731 ShouldNotReachHere();
duke@0 1732 }
duke@0 1733 } else if (code == lir_cmp_l2i) {
duke@0 1734 __ lcmp(left->as_register_hi(), left->as_register_lo(),
duke@0 1735 right->as_register_hi(), right->as_register_lo(),
duke@0 1736 dst->as_register());
duke@0 1737 } else {
duke@0 1738 ShouldNotReachHere();
duke@0 1739 }
duke@0 1740 }
duke@0 1741
duke@0 1742
duke@0 1743 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
duke@0 1744
duke@0 1745 Assembler::Condition acond;
duke@0 1746 switch (condition) {
duke@0 1747 case lir_cond_equal: acond = Assembler::equal; break;
duke@0 1748 case lir_cond_notEqual: acond = Assembler::notEqual; break;
duke@0 1749 case lir_cond_less: acond = Assembler::less; break;
duke@0 1750 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
duke@0 1751 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
duke@0 1752 case lir_cond_greater: acond = Assembler::greater; break;
duke@0 1753 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
duke@0 1754 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
duke@0 1755 default: ShouldNotReachHere();
duke@0 1756 };
duke@0 1757
duke@0 1758 if (opr1->is_constant() && opr1->type() == T_INT) {
duke@0 1759 Register dest = result->as_register();
duke@0 1760 // load up first part of constant before branch
duke@0 1761 // and do the rest in the delay slot.
duke@0 1762 if (!Assembler::is_simm13(opr1->as_jint())) {
duke@0 1763 __ sethi(opr1->as_jint(), dest);
duke@0 1764 }
duke@0 1765 } else if (opr1->is_constant()) {
duke@0 1766 const2reg(opr1, result, lir_patch_none, NULL);
duke@0 1767 } else if (opr1->is_register()) {
duke@0 1768 reg2reg(opr1, result);
duke@0 1769 } else if (opr1->is_stack()) {
duke@0 1770 stack2reg(opr1, result, result->type());
duke@0 1771 } else {
duke@0 1772 ShouldNotReachHere();
duke@0 1773 }
duke@0 1774 Label skip;
duke@0 1775 __ br(acond, false, Assembler::pt, skip);
duke@0 1776 if (opr1->is_constant() && opr1->type() == T_INT) {
duke@0 1777 Register dest = result->as_register();
duke@0 1778 if (Assembler::is_simm13(opr1->as_jint())) {
duke@0 1779 __ delayed()->or3(G0, opr1->as_jint(), dest);
duke@0 1780 } else {
duke@0 1781 // the sethi has been done above, so just put in the low 10 bits
duke@0 1782 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
duke@0 1783 }
duke@0 1784 } else {
duke@0 1785 // can't do anything useful in the delay slot
duke@0 1786 __ delayed()->nop();
duke@0 1787 }
duke@0 1788 if (opr2->is_constant()) {
duke@0 1789 const2reg(opr2, result, lir_patch_none, NULL);
duke@0 1790 } else if (opr2->is_register()) {
duke@0 1791 reg2reg(opr2, result);
duke@0 1792 } else if (opr2->is_stack()) {
duke@0 1793 stack2reg(opr2, result, result->type());
duke@0 1794 } else {
duke@0 1795 ShouldNotReachHere();
duke@0 1796 }
duke@0 1797 __ bind(skip);
duke@0 1798 }
duke@0 1799
duke@0 1800
duke@0 1801 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
duke@0 1802 assert(info == NULL, "unused on this code path");
duke@0 1803 assert(left->is_register(), "wrong items state");
duke@0 1804 assert(dest->is_register(), "wrong items state");
duke@0 1805
duke@0 1806 if (right->is_register()) {
duke@0 1807 if (dest->is_float_kind()) {
duke@0 1808
duke@0 1809 FloatRegister lreg, rreg, res;
duke@0 1810 FloatRegisterImpl::Width w;
duke@0 1811 if (right->is_single_fpu()) {
duke@0 1812 w = FloatRegisterImpl::S;
duke@0 1813 lreg = left->as_float_reg();
duke@0 1814 rreg = right->as_float_reg();
duke@0 1815 res = dest->as_float_reg();
duke@0 1816 } else {
duke@0 1817 w = FloatRegisterImpl::D;
duke@0 1818 lreg = left->as_double_reg();
duke@0 1819 rreg = right->as_double_reg();
duke@0 1820 res = dest->as_double_reg();
duke@0 1821 }
duke@0 1822
duke@0 1823 switch (code) {
duke@0 1824 case lir_add: __ fadd(w, lreg, rreg, res); break;
duke@0 1825 case lir_sub: __ fsub(w, lreg, rreg, res); break;
duke@0 1826 case lir_mul: // fall through
duke@0 1827 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
duke@0 1828 case lir_div: // fall through
duke@0 1829 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
duke@0 1830 default: ShouldNotReachHere();
duke@0 1831 }
duke@0 1832
duke@0 1833 } else if (dest->is_double_cpu()) {
duke@0 1834 #ifdef _LP64
duke@0 1835 Register dst_lo = dest->as_register_lo();
duke@0 1836 Register op1_lo = left->as_pointer_register();
duke@0 1837 Register op2_lo = right->as_pointer_register();
duke@0 1838
duke@0 1839 switch (code) {
duke@0 1840 case lir_add:
duke@0 1841 __ add(op1_lo, op2_lo, dst_lo);
duke@0 1842 break;
duke@0 1843
duke@0 1844 case lir_sub:
duke@0 1845 __ sub(op1_lo, op2_lo, dst_lo);
duke@0 1846 break;
duke@0 1847
duke@0 1848 default: ShouldNotReachHere();
duke@0 1849 }
duke@0 1850 #else
duke@0 1851 Register op1_lo = left->as_register_lo();
duke@0 1852 Register op1_hi = left->as_register_hi();
duke@0 1853 Register op2_lo = right->as_register_lo();
duke@0 1854 Register op2_hi = right->as_register_hi();
duke@0 1855 Register dst_lo = dest->as_register_lo();
duke@0 1856 Register dst_hi = dest->as_register_hi();
duke@0 1857
duke@0 1858 switch (code) {
duke@0 1859 case lir_add:
duke@0 1860 __ addcc(op1_lo, op2_lo, dst_lo);
duke@0 1861 __ addc (op1_hi, op2_hi, dst_hi);
duke@0 1862 break;
duke@0 1863
duke@0 1864 case lir_sub:
duke@0 1865 __ subcc(op1_lo, op2_lo, dst_lo);
duke@0 1866 __ subc (op1_hi, op2_hi, dst_hi);
duke@0 1867 break;
duke@0 1868
duke@0 1869 default: ShouldNotReachHere();
duke@0 1870 }
duke@0 1871 #endif
duke@0 1872 } else {
duke@0 1873 assert (right->is_single_cpu(), "Just Checking");
duke@0 1874
duke@0 1875 Register lreg = left->as_register();
duke@0 1876 Register res = dest->as_register();
duke@0 1877 Register rreg = right->as_register();
duke@0 1878 switch (code) {
duke@0 1879 case lir_add: __ add (lreg, rreg, res); break;
duke@0 1880 case lir_sub: __ sub (lreg, rreg, res); break;
duke@0 1881 case lir_mul: __ mult (lreg, rreg, res); break;
duke@0 1882 default: ShouldNotReachHere();
duke@0 1883 }
duke@0 1884 }
duke@0 1885 } else {
duke@0 1886 assert (right->is_constant(), "must be constant");
duke@0 1887
duke@0 1888 if (dest->is_single_cpu()) {
duke@0 1889 Register lreg = left->as_register();
duke@0 1890 Register res = dest->as_register();
duke@0 1891 int simm13 = right->as_constant_ptr()->as_jint();
duke@0 1892
duke@0 1893 switch (code) {
duke@0 1894 case lir_add: __ add (lreg, simm13, res); break;
duke@0 1895 case lir_sub: __ sub (lreg, simm13, res); break;
duke@0 1896 case lir_mul: __ mult (lreg, simm13, res); break;
duke@0 1897 default: ShouldNotReachHere();
duke@0 1898 }
duke@0 1899 } else {
duke@0 1900 Register lreg = left->as_pointer_register();
duke@0 1901 Register res = dest->as_register_lo();
duke@0 1902 long con = right->as_constant_ptr()->as_jlong();
duke@0 1903 assert(Assembler::is_simm13(con), "must be simm13");
duke@0 1904
duke@0 1905 switch (code) {
duke@0 1906 case lir_add: __ add (lreg, (int)con, res); break;
duke@0 1907 case lir_sub: __ sub (lreg, (int)con, res); break;
duke@0 1908 case lir_mul: __ mult (lreg, (int)con, res); break;
duke@0 1909 default: ShouldNotReachHere();
duke@0 1910 }
duke@0 1911 }
duke@0 1912 }
duke@0 1913 }
duke@0 1914
duke@0 1915
duke@0 1916 void LIR_Assembler::fpop() {
duke@0 1917 // do nothing
duke@0 1918 }
duke@0 1919
duke@0 1920
duke@0 1921 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
duke@0 1922 switch (code) {
duke@0 1923 case lir_sin:
duke@0 1924 case lir_tan:
duke@0 1925 case lir_cos: {
duke@0 1926 assert(thread->is_valid(), "preserve the thread object for performance reasons");
duke@0 1927 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
duke@0 1928 break;
duke@0 1929 }
duke@0 1930 case lir_sqrt: {
duke@0 1931 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
duke@0 1932 FloatRegister src_reg = value->as_double_reg();
duke@0 1933 FloatRegister dst_reg = dest->as_double_reg();
duke@0 1934 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
duke@0 1935 break;
duke@0 1936 }
duke@0 1937 case lir_abs: {
duke@0 1938 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
duke@0 1939 FloatRegister src_reg = value->as_double_reg();
duke@0 1940 FloatRegister dst_reg = dest->as_double_reg();
duke@0 1941 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
duke@0 1942 break;
duke@0 1943 }
duke@0 1944 default: {
duke@0 1945 ShouldNotReachHere();
duke@0 1946 break;
duke@0 1947 }
duke@0 1948 }
duke@0 1949 }
duke@0 1950
duke@0 1951
duke@0 1952 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
duke@0 1953 if (right->is_constant()) {
duke@0 1954 if (dest->is_single_cpu()) {
duke@0 1955 int simm13 = right->as_constant_ptr()->as_jint();
duke@0 1956 switch (code) {
duke@0 1957 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
duke@0 1958 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
duke@0 1959 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
duke@0 1960 default: ShouldNotReachHere();
duke@0 1961 }
duke@0 1962 } else {
duke@0 1963 long c = right->as_constant_ptr()->as_jlong();
duke@0 1964 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
duke@0 1965 int simm13 = (int)c;
duke@0 1966 switch (code) {
duke@0 1967 case lir_logic_and:
duke@0 1968 #ifndef _LP64
duke@0 1969 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
duke@0 1970 #endif
duke@0 1971 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
duke@0 1972 break;
duke@0 1973
duke@0 1974 case lir_logic_or:
duke@0 1975 #ifndef _LP64
duke@0 1976 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
duke@0 1977 #endif
duke@0 1978 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
duke@0 1979 break;
duke@0 1980
duke@0 1981 case lir_logic_xor:
duke@0 1982 #ifndef _LP64
duke@0 1983 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
duke@0 1984 #endif
duke@0 1985 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
duke@0 1986 break;
duke@0 1987
duke@0 1988 default: ShouldNotReachHere();
duke@0 1989 }
duke@0 1990 }
duke@0 1991 } else {
duke@0 1992 assert(right->is_register(), "right should be in register");
duke@0 1993
duke@0 1994 if (dest->is_single_cpu()) {
duke@0 1995 switch (code) {
duke@0 1996 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
duke@0 1997 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
duke@0 1998 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
duke@0 1999 default: ShouldNotReachHere();
duke@0 2000 }
duke@0 2001 } else {
duke@0 2002 #ifdef _LP64
duke@0 2003 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
duke@0 2004 left->as_register_lo();
duke@0 2005 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
duke@0 2006 right->as_register_lo();
duke@0 2007
duke@0 2008 switch (code) {
duke@0 2009 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
duke@0 2010 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
duke@0 2011 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
duke@0 2012 default: ShouldNotReachHere();
duke@0 2013 }
duke@0 2014 #else
duke@0 2015 switch (code) {
duke@0 2016 case lir_logic_and:
duke@0 2017 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
duke@0 2018 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
duke@0 2019 break;
duke@0 2020
duke@0 2021 case lir_logic_or:
duke@0 2022 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
duke@0 2023 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
duke@0 2024 break;
duke@0 2025
duke@0 2026 case lir_logic_xor:
duke@0 2027 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
duke@0 2028 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
duke@0 2029 break;
duke@0 2030
duke@0 2031 default: ShouldNotReachHere();
duke@0 2032 }
duke@0 2033 #endif
duke@0 2034 }
duke@0 2035 }
duke@0 2036 }
duke@0 2037
duke@0 2038
duke@0 2039 int LIR_Assembler::shift_amount(BasicType t) {
duke@0 2040 int elem_size = type2aelembytes[t];
duke@0 2041 switch (elem_size) {
duke@0 2042 case 1 : return 0;
duke@0 2043 case 2 : return 1;
duke@0 2044 case 4 : return 2;
duke@0 2045 case 8 : return 3;
duke@0 2046 }
duke@0 2047 ShouldNotReachHere();
duke@0 2048 return -1;
duke@0 2049 }
duke@0 2050
duke@0 2051
duke@0 2052 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) {
duke@0 2053 assert(exceptionOop->as_register() == Oexception, "should match");
duke@0 2054 assert(unwind || exceptionPC->as_register() == Oissuing_pc, "should match");
duke@0 2055
duke@0 2056 info->add_register_oop(exceptionOop);
duke@0 2057
duke@0 2058 if (unwind) {
duke@0 2059 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
duke@0 2060 __ delayed()->nop();
duke@0 2061 } else {
duke@0 2062 // reuse the debug info from the safepoint poll for the throw op itself
duke@0 2063 address pc_for_athrow = __ pc();
duke@0 2064 int pc_for_athrow_offset = __ offset();
duke@0 2065 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
duke@0 2066 __ set((intptr_t)pc_for_athrow, Oissuing_pc, rspec);
duke@0 2067 add_call_info(pc_for_athrow_offset, info); // for exception handler
duke@0 2068
duke@0 2069 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
duke@0 2070 __ delayed()->nop();
duke@0 2071 }
duke@0 2072 }
duke@0 2073
duke@0 2074
duke@0 2075 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
duke@0 2076 Register src = op->src()->as_register();
duke@0 2077 Register dst = op->dst()->as_register();
duke@0 2078 Register src_pos = op->src_pos()->as_register();
duke@0 2079 Register dst_pos = op->dst_pos()->as_register();
duke@0 2080 Register length = op->length()->as_register();
duke@0 2081 Register tmp = op->tmp()->as_register();
duke@0 2082 Register tmp2 = O7;
duke@0 2083
duke@0 2084 int flags = op->flags();
duke@0 2085 ciArrayKlass* default_type = op->expected_type();
duke@0 2086 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
duke@0 2087 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
duke@0 2088
duke@0 2089 // set up the arraycopy stub information
duke@0 2090 ArrayCopyStub* stub = op->stub();
duke@0 2091
duke@0 2092 // always do stub if no type information is available. it's ok if
duke@0 2093 // the known type isn't loaded since the code sanity checks
duke@0 2094 // in debug mode and the type isn't required when we know the exact type
duke@0 2095 // also check that the type is an array type.
duke@0 2096 if (op->expected_type() == NULL) {
duke@0 2097 __ mov(src, O0);
duke@0 2098 __ mov(src_pos, O1);
duke@0 2099 __ mov(dst, O2);
duke@0 2100 __ mov(dst_pos, O3);
duke@0 2101 __ mov(length, O4);
duke@0 2102 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
duke@0 2103
duke@0 2104 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry());
duke@0 2105 __ delayed()->nop();
duke@0 2106 __ bind(*stub->continuation());
duke@0 2107 return;
duke@0 2108 }
duke@0 2109
duke@0 2110 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
duke@0 2111
duke@0 2112 // make sure src and dst are non-null and load array length
duke@0 2113 if (flags & LIR_OpArrayCopy::src_null_check) {
duke@0 2114 __ tst(src);
duke@0 2115 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
duke@0 2116 __ delayed()->nop();
duke@0 2117 }
duke@0 2118
duke@0 2119 if (flags & LIR_OpArrayCopy::dst_null_check) {
duke@0 2120 __ tst(dst);
duke@0 2121 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
duke@0 2122 __ delayed()->nop();
duke@0 2123 }
duke@0 2124
duke@0 2125 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
duke@0 2126 // test src_pos register
duke@0 2127 __ tst(src_pos);
duke@0 2128 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
duke@0 2129 __ delayed()->nop();
duke@0 2130 }
duke@0 2131
duke@0 2132 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
duke@0 2133 // test dst_pos register
duke@0 2134 __ tst(dst_pos);
duke@0 2135 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
duke@0 2136 __ delayed()->nop();
duke@0 2137 }
duke@0 2138
duke@0 2139 if (flags & LIR_OpArrayCopy::length_positive_check) {
duke@0 2140 // make sure length isn't negative
duke@0 2141 __ tst(length);
duke@0 2142 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
duke@0 2143 __ delayed()->nop();
duke@0 2144 }
duke@0 2145
duke@0 2146 if (flags & LIR_OpArrayCopy::src_range_check) {
duke@0 2147 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
duke@0 2148 __ add(length, src_pos, tmp);
duke@0 2149 __ cmp(tmp2, tmp);
duke@0 2150 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
duke@0 2151 __ delayed()->nop();
duke@0 2152 }
duke@0 2153
duke@0 2154 if (flags & LIR_OpArrayCopy::dst_range_check) {
duke@0 2155 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
duke@0 2156 __ add(length, dst_pos, tmp);
duke@0 2157 __ cmp(tmp2, tmp);
duke@0 2158 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
duke@0 2159 __ delayed()->nop();
duke@0 2160 }
duke@0 2161
duke@0 2162 if (flags & LIR_OpArrayCopy::type_check) {
duke@0 2163 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
duke@0 2164 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
duke@0 2165 __ cmp(tmp, tmp2);
duke@0 2166 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
duke@0 2167 __ delayed()->nop();
duke@0 2168 }
duke@0 2169
duke@0 2170 #ifdef ASSERT
duke@0 2171 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
duke@0 2172 // Sanity check the known type with the incoming class. For the
duke@0 2173 // primitive case the types must match exactly with src.klass and
duke@0 2174 // dst.klass each exactly matching the default type. For the
duke@0 2175 // object array case, if no type check is needed then either the
duke@0 2176 // dst type is exactly the expected type and the src type is a
duke@0 2177 // subtype which we can't check or src is the same array as dst
duke@0 2178 // but not necessarily exactly of type default_type.
duke@0 2179 Label known_ok, halt;
duke@0 2180 jobject2reg(op->expected_type()->encoding(), tmp);
duke@0 2181 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
duke@0 2182 if (basic_type != T_OBJECT) {
duke@0 2183 __ cmp(tmp, tmp2);
duke@0 2184 __ br(Assembler::notEqual, false, Assembler::pn, halt);
duke@0 2185 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
duke@0 2186 __ cmp(tmp, tmp2);
duke@0 2187 __ br(Assembler::equal, false, Assembler::pn, known_ok);
duke@0 2188 __ delayed()->nop();
duke@0 2189 } else {
duke@0 2190 __ cmp(tmp, tmp2);
duke@0 2191 __ br(Assembler::equal, false, Assembler::pn, known_ok);
duke@0 2192 __ delayed()->cmp(src, dst);
duke@0 2193 __ br(Assembler::equal, false, Assembler::pn, known_ok);
duke@0 2194 __ delayed()->nop();
duke@0 2195 }
duke@0 2196 __ bind(halt);
duke@0 2197 __ stop("incorrect type information in arraycopy");
duke@0 2198 __ bind(known_ok);
duke@0 2199 }
duke@0 2200 #endif
duke@0 2201
duke@0 2202 int shift = shift_amount(basic_type);
duke@0 2203
duke@0 2204 Register src_ptr = O0;
duke@0 2205 Register dst_ptr = O1;
duke@0 2206 Register len = O2;
duke@0 2207
duke@0 2208 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
duke@0 2209 if (shift == 0) {
duke@0 2210 __ add(src_ptr, src_pos, src_ptr);
duke@0 2211 } else {
duke@0 2212 __ sll(src_pos, shift, tmp);
duke@0 2213 __ add(src_ptr, tmp, src_ptr);
duke@0 2214 }
duke@0 2215
duke@0 2216 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
duke@0 2217 if (shift == 0) {
duke@0 2218 __ add(dst_ptr, dst_pos, dst_ptr);
duke@0 2219 } else {
duke@0 2220 __ sll(dst_pos, shift, tmp);
duke@0 2221 __ add(dst_ptr, tmp, dst_ptr);
duke@0 2222 }
duke@0 2223
duke@0 2224 if (basic_type != T_OBJECT) {
duke@0 2225 if (shift == 0) {
duke@0 2226 __ mov(length, len);
duke@0 2227 } else {
duke@0 2228 __ sll(length, shift, len);
duke@0 2229 }
duke@0 2230 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy));
duke@0 2231 } else {
duke@0 2232 // oop_arraycopy takes a length in number of elements, so don't scale it.
duke@0 2233 __ mov(length, len);
duke@0 2234 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy));
duke@0 2235 }
duke@0 2236
duke@0 2237 __ bind(*stub->continuation());
duke@0 2238 }
duke@0 2239
duke@0 2240
duke@0 2241 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
duke@0 2242 if (dest->is_single_cpu()) {
duke@0 2243 #ifdef _LP64
duke@0 2244 if (left->type() == T_OBJECT) {
duke@0 2245 switch (code) {
duke@0 2246 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
duke@0 2247 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
duke@0 2248 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
duke@0 2249 default: ShouldNotReachHere();
duke@0 2250 }
duke@0 2251 } else
duke@0 2252 #endif
duke@0 2253 switch (code) {
duke@0 2254 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
duke@0 2255 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
duke@0 2256 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
duke@0 2257 default: ShouldNotReachHere();
duke@0 2258 }
duke@0 2259 } else {
duke@0 2260 #ifdef _LP64
duke@0 2261 switch (code) {
duke@0 2262 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
duke@0 2263 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
duke@0 2264 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
duke@0 2265 default: ShouldNotReachHere();
duke@0 2266 }
duke@0 2267 #else
duke@0 2268 switch (code) {
duke@0 2269 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
duke@0 2270 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
duke@0 2271 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
duke@0 2272 default: ShouldNotReachHere();
duke@0 2273 }
duke@0 2274 #endif
duke@0 2275 }
duke@0 2276 }
duke@0 2277
duke@0 2278
duke@0 2279 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
duke@0 2280 #ifdef _LP64
duke@0 2281 if (left->type() == T_OBJECT) {
duke@0 2282 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
duke@0 2283 Register l = left->as_register();
duke@0 2284 Register d = dest->as_register_lo();
duke@0 2285 switch (code) {
duke@0 2286 case lir_shl: __ sllx (l, count, d); break;
duke@0 2287 case lir_shr: __ srax (l, count, d); break;
duke@0 2288 case lir_ushr: __ srlx (l, count, d); break;
duke@0 2289 default: ShouldNotReachHere();
duke@0 2290 }
duke@0 2291 return;
duke@0 2292 }
duke@0 2293 #endif
duke@0 2294
duke@0 2295 if (dest->is_single_cpu()) {
duke@0 2296 count = count & 0x1F; // Java spec
duke@0 2297 switch (code) {
duke@0 2298 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
duke@0 2299 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
duke@0 2300 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
duke@0 2301 default: ShouldNotReachHere();
duke@0 2302 }
duke@0 2303 } else if (dest->is_double_cpu()) {
duke@0 2304 count = count & 63; // Java spec
duke@0 2305 switch (code) {
duke@0 2306 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
duke@0 2307 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
duke@0 2308 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
duke@0 2309 default: ShouldNotReachHere();
duke@0 2310 }
duke@0 2311 } else {
duke@0 2312 ShouldNotReachHere();
duke@0 2313 }
duke@0 2314 }
duke@0 2315
duke@0 2316
duke@0 2317 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
duke@0 2318 assert(op->tmp1()->as_register() == G1 &&
duke@0 2319 op->tmp2()->as_register() == G3 &&
duke@0 2320 op->tmp3()->as_register() == G4 &&
duke@0 2321 op->obj()->as_register() == O0 &&
duke@0 2322 op->klass()->as_register() == G5, "must be");
duke@0 2323 if (op->init_check()) {
duke@0 2324 __ ld(op->klass()->as_register(),
duke@0 2325 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc),
duke@0 2326 op->tmp1()->as_register());
duke@0 2327 add_debug_info_for_null_check_here(op->stub()->info());
duke@0 2328 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized);
duke@0 2329 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
duke@0 2330 __ delayed()->nop();
duke@0 2331 }
duke@0 2332 __ allocate_object(op->obj()->as_register(),
duke@0 2333 op->tmp1()->as_register(),
duke@0 2334 op->tmp2()->as_register(),
duke@0 2335 op->tmp3()->as_register(),
duke@0 2336 op->header_size(),
duke@0 2337 op->object_size(),
duke@0 2338 op->klass()->as_register(),
duke@0 2339 *op->stub()->entry());
duke@0 2340 __ bind(*op->stub()->continuation());
duke@0 2341 __ verify_oop(op->obj()->as_register());
duke@0 2342 }
duke@0 2343
duke@0 2344
duke@0 2345 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
duke@0 2346 assert(op->tmp1()->as_register() == G1 &&
duke@0 2347 op->tmp2()->as_register() == G3 &&
duke@0 2348 op->tmp3()->as_register() == G4 &&
duke@0 2349 op->tmp4()->as_register() == O1 &&
duke@0 2350 op->klass()->as_register() == G5, "must be");
duke@0 2351 if (UseSlowPath ||
duke@0 2352 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
duke@0 2353 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
duke@0 2354 __ br(Assembler::always, false, Assembler::pn, *op->stub()->entry());
duke@0 2355 __ delayed()->nop();
duke@0 2356 } else {
duke@0 2357 __ allocate_array(op->obj()->as_register(),
duke@0 2358 op->len()->as_register(),
duke@0 2359 op->tmp1()->as_register(),
duke@0 2360 op->tmp2()->as_register(),
duke@0 2361 op->tmp3()->as_register(),
duke@0 2362 arrayOopDesc::header_size(op->type()),
duke@0 2363 type2aelembytes[op->type()],
duke@0 2364 op->klass()->as_register(),
duke@0 2365 *op->stub()->entry());
duke@0 2366 }
duke@0 2367 __ bind(*op->stub()->continuation());
duke@0 2368 }
duke@0 2369
duke@0 2370
duke@0 2371 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
duke@0 2372 LIR_Code code = op->code();
duke@0 2373 if (code == lir_store_check) {
duke@0 2374 Register value = op->object()->as_register();
duke@0 2375 Register array = op->array()->as_register();
duke@0 2376 Register k_RInfo = op->tmp1()->as_register();
duke@0 2377 Register klass_RInfo = op->tmp2()->as_register();
duke@0 2378 Register Rtmp1 = op->tmp3()->as_register();
duke@0 2379
duke@0 2380 __ verify_oop(value);
duke@0 2381
duke@0 2382 CodeStub* stub = op->stub();
duke@0 2383 Label done;
duke@0 2384 __ cmp(value, 0);
duke@0 2385 __ br(Assembler::equal, false, Assembler::pn, done);
duke@0 2386 __ delayed()->nop();
duke@0 2387 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
duke@0 2388 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
duke@0 2389
duke@0 2390 // get instance klass
duke@0 2391 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
duke@0 2392 // get super_check_offset
duke@0 2393 load(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes(), Rtmp1, T_INT, NULL);
duke@0 2394 // See if we get an immediate positive hit
duke@0 2395 __ ld_ptr(klass_RInfo, Rtmp1, FrameMap::O7_oop_opr->as_register());
duke@0 2396 __ cmp(k_RInfo, O7);
duke@0 2397 __ br(Assembler::equal, false, Assembler::pn, done);
duke@0 2398 __ delayed()->nop();
duke@0 2399 // check for immediate negative hit
duke@0 2400 __ cmp(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
duke@0 2401 __ br(Assembler::notEqual, false, Assembler::pn, *stub->entry());
duke@0 2402 __ delayed()->nop();
duke@0 2403 // check for self
duke@0 2404 __ cmp(klass_RInfo, k_RInfo);
duke@0 2405 __ br(Assembler::equal, false, Assembler::pn, done);
duke@0 2406 __ delayed()->nop();
duke@0 2407
duke@0 2408 // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup");
duke@0 2409 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
duke@0 2410 __ delayed()->nop();
duke@0 2411 __ cmp(G3, 0);
duke@0 2412 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
duke@0 2413 __ delayed()->nop();
duke@0 2414 __ bind(done);
duke@0 2415 } else if (op->code() == lir_checkcast) {
duke@0 2416 // we always need a stub for the failure case.
duke@0 2417 CodeStub* stub = op->stub();
duke@0 2418 Register obj = op->object()->as_register();
duke@0 2419 Register k_RInfo = op->tmp1()->as_register();
duke@0 2420 Register klass_RInfo = op->tmp2()->as_register();
duke@0 2421 Register dst = op->result_opr()->as_register();
duke@0 2422 Register Rtmp1 = op->tmp3()->as_register();
duke@0 2423 ciKlass* k = op->klass();
duke@0 2424
duke@0 2425 if (obj == k_RInfo) {
duke@0 2426 k_RInfo = klass_RInfo;
duke@0 2427 klass_RInfo = obj;
duke@0 2428 }
duke@0 2429 if (op->profiled_method() != NULL) {
duke@0 2430 ciMethod* method = op->profiled_method();
duke@0 2431 int bci = op->profiled_bci();
duke@0 2432
duke@0 2433 // We need two temporaries to perform this operation on SPARC,
duke@0 2434 // so to keep things simple we perform a redundant test here
duke@0 2435 Label profile_done;
duke@0 2436 __ cmp(obj, 0);
duke@0 2437 __ br(Assembler::notEqual, false, Assembler::pn, profile_done);
duke@0 2438 __ delayed()->nop();
duke@0 2439 // Object is null; update methodDataOop
duke@0 2440 ciMethodData* md = method->method_data();
duke@0 2441 if (md == NULL) {
duke@0 2442 bailout("out of memory building methodDataOop");
duke@0 2443 return;
duke@0 2444 }
duke@0 2445 ciProfileData* data = md->bci_to_data(bci);
duke@0 2446 assert(data != NULL, "need data for checkcast");
duke@0 2447 assert(data->is_BitData(), "need BitData for checkcast");
duke@0 2448 Register mdo = k_RInfo;
duke@0 2449 Register data_val = Rtmp1;
duke@0 2450 jobject2reg(md->encoding(), mdo);
duke@0 2451
duke@0 2452 int mdo_offset_bias = 0;
duke@0 2453 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
duke@0 2454 // The offset is large so bias the mdo by the base of the slot so
duke@0 2455 // that the ld can use simm13s to reference the slots of the data
duke@0 2456 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
duke@0 2457 __ set(mdo_offset_bias, data_val);
duke@0 2458 __ add(mdo, data_val, mdo);
duke@0 2459 }
duke@0 2460
duke@0 2461
duke@0 2462 Address flags_addr(mdo, 0, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
duke@0 2463 __ ldub(flags_addr, data_val);
duke@0 2464 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
duke@0 2465 __ stb(data_val, flags_addr);
duke@0 2466 __ bind(profile_done);
duke@0 2467 }
duke@0 2468
duke@0 2469 Label done;
duke@0 2470 // patching may screw with our temporaries on sparc,
duke@0 2471 // so let's do it before loading the class
duke@0 2472 if (k->is_loaded()) {
duke@0 2473 jobject2reg(k->encoding(), k_RInfo);
duke@0 2474 } else {
duke@0 2475 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
duke@0 2476 }
duke@0 2477 assert(obj != k_RInfo, "must be different");
duke@0 2478 __ cmp(obj, 0);
duke@0 2479 __ br(Assembler::equal, false, Assembler::pn, done);
duke@0 2480 __ delayed()->nop();
duke@0 2481
duke@0 2482 // get object class
duke@0 2483 // not a safepoint as obj null check happens earlier
duke@0 2484 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
duke@0 2485 if (op->fast_check()) {
duke@0 2486 assert_different_registers(klass_RInfo, k_RInfo);
duke@0 2487 __ cmp(k_RInfo, klass_RInfo);
duke@0 2488 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
duke@0 2489 __ delayed()->nop();
duke@0 2490 __ bind(done);
duke@0 2491 } else {
duke@0 2492 if (k->is_loaded()) {
duke@0 2493 load(klass_RInfo, k->super_check_offset(), Rtmp1, T_OBJECT, NULL);
duke@0 2494
duke@0 2495 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
duke@0 2496 // See if we get an immediate positive hit
duke@0 2497 __ cmp(Rtmp1, k_RInfo );
duke@0 2498 __ br(Assembler::notEqual, false, Assembler::pn, *stub->entry());
duke@0 2499 __ delayed()->nop();
duke@0 2500 } else {
duke@0 2501 // See if we get an immediate positive hit
duke@0 2502 assert_different_registers(Rtmp1, k_RInfo, klass_RInfo);
duke@0 2503 __ cmp(Rtmp1, k_RInfo );
duke@0 2504 __ br(Assembler::equal, false, Assembler::pn, done);
duke@0 2505 // check for self
duke@0 2506 __ delayed()->cmp(klass_RInfo, k_RInfo);
duke@0 2507 __ br(Assembler::equal, false, Assembler::pn, done);
duke@0 2508 __ delayed()->nop();
duke@0 2509
duke@0 2510 // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup");
duke@0 2511 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
duke@0 2512 __ delayed()->nop();
duke@0 2513 __ cmp(G3, 0);
duke@0 2514 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
duke@0 2515 __ delayed()->nop();
duke@0 2516 }
duke@0 2517 __ bind(done);
duke@0 2518 } else {
duke@0 2519 assert_different_registers(Rtmp1, klass_RInfo, k_RInfo);
duke@0 2520
duke@0 2521 load(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes(), Rtmp1, T_INT, NULL);
duke@0 2522 // See if we get an immediate positive hit
duke@0 2523 load(klass_RInfo, Rtmp1, FrameMap::O7_oop_opr, T_OBJECT);
duke@0 2524 __ cmp(k_RInfo, O7);
duke@0 2525 __ br(Assembler::equal, false, Assembler::pn, done);
duke@0 2526 __ delayed()->nop();
duke@0 2527 // check for immediate negative hit
duke@0 2528 __ cmp(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
duke@0 2529 __ br(Assembler::notEqual, false, Assembler::pn, *stub->entry());
duke@0 2530 // check for self
duke@0 2531 __ delayed()->cmp(klass_RInfo, k_RInfo);
duke@0 2532 __ br(Assembler::equal, false, Assembler::pn, done);
duke@0 2533 __ delayed()->nop();
duke@0 2534
duke@0 2535 // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup");
duke@0 2536 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
duke@0 2537 __ delayed()->nop();
duke@0 2538 __ cmp(G3, 0);
duke@0 2539 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
duke@0 2540 __ delayed()->nop();
duke@0 2541 __ bind(done);
duke@0 2542 }
duke@0 2543
duke@0 2544 }
duke@0 2545 __ mov(obj, dst);
duke@0 2546 } else if (code == lir_instanceof) {
duke@0 2547 Register obj = op->object()->as_register();
duke@0 2548 Register k_RInfo = op->tmp1()->as_register();
duke@0 2549 Register klass_RInfo = op->tmp2()->as_register();
duke@0 2550 Register dst = op->result_opr()->as_register();
duke@0 2551 Register Rtmp1 = op->tmp3()->as_register();
duke@0 2552 ciKlass* k = op->klass();
duke@0 2553
duke@0 2554 Label done;
duke@0 2555 if (obj == k_RInfo) {
duke@0 2556 k_RInfo = klass_RInfo;
duke@0 2557 klass_RInfo = obj;
duke@0 2558 }
duke@0 2559 // patching may screw with our temporaries on sparc,
duke@0 2560 // so let's do it before loading the class
duke@0 2561 if (k->is_loaded()) {
duke@0 2562 jobject2reg(k->encoding(), k_RInfo);
duke@0 2563 } else {
duke@0 2564 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
duke@0 2565 }
duke@0 2566 assert(obj != k_RInfo, "must be different");
duke@0 2567 __ cmp(obj, 0);
duke@0 2568 __ br(Assembler::equal, true, Assembler::pn, done);
duke@0 2569 __ delayed()->set(0, dst);
duke@0 2570
duke@0 2571 // get object class
duke@0 2572 // not a safepoint as obj null check happens earlier
duke@0 2573 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
duke@0 2574 if (op->fast_check()) {
duke@0 2575 __ cmp(k_RInfo, klass_RInfo);
duke@0 2576 __ br(Assembler::equal, true, Assembler::pt, done);
duke@0 2577 __ delayed()->set(1, dst);
duke@0 2578 __ set(0, dst);
duke@0 2579 __ bind(done);
duke@0 2580 } else {
duke@0 2581 if (k->is_loaded()) {
duke@0 2582 assert_different_registers(Rtmp1, klass_RInfo, k_RInfo);
duke@0 2583 load(klass_RInfo, k->super_check_offset(), Rtmp1, T_OBJECT, NULL);
duke@0 2584
duke@0 2585 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
duke@0 2586 // See if we get an immediate positive hit
duke@0 2587 __ cmp(Rtmp1, k_RInfo );
duke@0 2588 __ br(Assembler::equal, true, Assembler::pt, done);
duke@0 2589 __ delayed()->set(1, dst);
duke@0 2590 __ set(0, dst);
duke@0 2591 __ bind(done);
duke@0 2592 } else {
duke@0 2593 // See if we get an immediate positive hit
duke@0 2594 assert_different_registers(Rtmp1, k_RInfo, klass_RInfo);
duke@0 2595 __ cmp(Rtmp1, k_RInfo );
duke@0 2596 __ br(Assembler::equal, true, Assembler::pt, done);
duke@0 2597 __ delayed()->set(1, dst);
duke@0 2598 // check for self
duke@0 2599 __ cmp(klass_RInfo, k_RInfo);
duke@0 2600 __ br(Assembler::equal, true, Assembler::pt, done);
duke@0 2601 __ delayed()->set(1, dst);
duke@0 2602
duke@0 2603 // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup");
duke@0 2604 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
duke@0 2605 __ delayed()->nop();
duke@0 2606 __ mov(G3, dst);
duke@0 2607 __ bind(done);
duke@0 2608 }
duke@0 2609 } else {
duke@0 2610 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
duke@0 2611
duke@0 2612 load(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes(), dst, T_INT, NULL);
duke@0 2613 // See if we get an immediate positive hit
duke@0 2614 load(klass_RInfo, dst, FrameMap::O7_oop_opr, T_OBJECT);
duke@0 2615 __ cmp(k_RInfo, O7);
duke@0 2616 __ br(Assembler::equal, true, Assembler::pt, done);
duke@0 2617 __ delayed()->set(1, dst);
duke@0 2618 // check for immediate negative hit
duke@0 2619 __ cmp(dst, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
duke@0 2620 __ br(Assembler::notEqual, true, Assembler::pt, done);
duke@0 2621 __ delayed()->set(0, dst);
duke@0 2622 // check for self
duke@0 2623 __ cmp(klass_RInfo, k_RInfo);
duke@0 2624 __ br(Assembler::equal, true, Assembler::pt, done);
duke@0 2625 __ delayed()->set(1, dst);
duke@0 2626
duke@0 2627 // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup");
duke@0 2628 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
duke@0 2629 __ delayed()->nop();
duke@0 2630 __ mov(G3, dst);
duke@0 2631 __ bind(done);
duke@0 2632 }
duke@0 2633 }
duke@0 2634 } else {
duke@0 2635 ShouldNotReachHere();
duke@0 2636 }
duke@0 2637
duke@0 2638 }
duke@0 2639
duke@0 2640
duke@0 2641 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
duke@0 2642 if (op->code() == lir_cas_long) {
duke@0 2643 assert(VM_Version::supports_cx8(), "wrong machine");
duke@0 2644 Register addr = op->addr()->as_pointer_register();
duke@0 2645 Register cmp_value_lo = op->cmp_value()->as_register_lo();
duke@0 2646 Register cmp_value_hi = op->cmp_value()->as_register_hi();
duke@0 2647 Register new_value_lo = op->new_value()->as_register_lo();
duke@0 2648 Register new_value_hi = op->new_value()->as_register_hi();
duke@0 2649 Register t1 = op->tmp1()->as_register();
duke@0 2650 Register t2 = op->tmp2()->as_register();
duke@0 2651 #ifdef _LP64
duke@0 2652 __ mov(cmp_value_lo, t1);
duke@0 2653 __ mov(new_value_lo, t2);
duke@0 2654 #else
duke@0 2655 // move high and low halves of long values into single registers
duke@0 2656 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
duke@0 2657 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
duke@0 2658 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
duke@0 2659 __ sllx(new_value_hi, 32, t2);
duke@0 2660 __ srl(new_value_lo, 0, new_value_lo);
duke@0 2661 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
duke@0 2662 #endif
duke@0 2663 // perform the compare and swap operation
duke@0 2664 __ casx(addr, t1, t2);
duke@0 2665 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
duke@0 2666 // overwritten with the original value in "addr" and will be equal to t1.
duke@0 2667 __ cmp(t1, t2);
duke@0 2668
duke@0 2669 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
duke@0 2670 Register addr = op->addr()->as_pointer_register();
duke@0 2671 Register cmp_value = op->cmp_value()->as_register();
duke@0 2672 Register new_value = op->new_value()->as_register();
duke@0 2673 Register t1 = op->tmp1()->as_register();
duke@0 2674 Register t2 = op->tmp2()->as_register();
duke@0 2675 __ mov(cmp_value, t1);
duke@0 2676 __ mov(new_value, t2);
duke@0 2677 #ifdef _LP64
duke@0 2678 if (op->code() == lir_cas_obj) {
duke@0 2679 __ casx(addr, t1, t2);
duke@0 2680 } else
duke@0 2681 #endif
duke@0 2682 {
duke@0 2683 __ cas(addr, t1, t2);
duke@0 2684 }
duke@0 2685 __ cmp(t1, t2);
duke@0 2686 } else {
duke@0 2687 Unimplemented();
duke@0 2688 }
duke@0 2689 }
duke@0 2690
duke@0 2691 void LIR_Assembler::set_24bit_FPU() {
duke@0 2692 Unimplemented();
duke@0 2693 }
duke@0 2694
duke@0 2695
duke@0 2696 void LIR_Assembler::reset_FPU() {
duke@0 2697 Unimplemented();
duke@0 2698 }
duke@0 2699
duke@0 2700
duke@0 2701 void LIR_Assembler::breakpoint() {
duke@0 2702 __ breakpoint_trap();
duke@0 2703 }
duke@0 2704
duke@0 2705
duke@0 2706 void LIR_Assembler::push(LIR_Opr opr) {
duke@0 2707 Unimplemented();
duke@0 2708 }
duke@0 2709
duke@0 2710
duke@0 2711 void LIR_Assembler::pop(LIR_Opr opr) {
duke@0 2712 Unimplemented();
duke@0 2713 }
duke@0 2714
duke@0 2715
duke@0 2716 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
duke@0 2717 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
duke@0 2718 Register dst = dst_opr->as_register();
duke@0 2719 Register reg = mon_addr.base();
duke@0 2720 int offset = mon_addr.disp();
duke@0 2721 // compute pointer to BasicLock
duke@0 2722 if (mon_addr.is_simm13()) {
duke@0 2723 __ add(reg, offset, dst);
duke@0 2724 } else {
duke@0 2725 __ set(offset, dst);
duke@0 2726 __ add(dst, reg, dst);
duke@0 2727 }
duke@0 2728 }
duke@0 2729
duke@0 2730
duke@0 2731 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
duke@0 2732 Register obj = op->obj_opr()->as_register();
duke@0 2733 Register hdr = op->hdr_opr()->as_register();
duke@0 2734 Register lock = op->lock_opr()->as_register();
duke@0 2735
duke@0 2736 // obj may not be an oop
duke@0 2737 if (op->code() == lir_lock) {
duke@0 2738 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
duke@0 2739 if (UseFastLocking) {
duke@0 2740 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
duke@0 2741 // add debug info for NullPointerException only if one is possible
duke@0 2742 if (op->info() != NULL) {
duke@0 2743 add_debug_info_for_null_check_here(op->info());
duke@0 2744 }
duke@0 2745 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
duke@0 2746 } else {
duke@0 2747 // always do slow locking
duke@0 2748 // note: the slow locking code could be inlined here, however if we use
duke@0 2749 // slow locking, speed doesn't matter anyway and this solution is
duke@0 2750 // simpler and requires less duplicated code - additionally, the
duke@0 2751 // slow locking code is the same in either case which simplifies
duke@0 2752 // debugging
duke@0 2753 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
duke@0 2754 __ delayed()->nop();
duke@0 2755 }
duke@0 2756 } else {
duke@0 2757 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
duke@0 2758 if (UseFastLocking) {
duke@0 2759 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
duke@0 2760 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
duke@0 2761 } else {
duke@0 2762 // always do slow unlocking
duke@0 2763 // note: the slow unlocking code could be inlined here, however if we use
duke@0 2764 // slow unlocking, speed doesn't matter anyway and this solution is
duke@0 2765 // simpler and requires less duplicated code - additionally, the
duke@0 2766 // slow unlocking code is the same in either case which simplifies
duke@0 2767 // debugging
duke@0 2768 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
duke@0 2769 __ delayed()->nop();
duke@0 2770 }
duke@0 2771 }
duke@0 2772 __ bind(*op->stub()->continuation());
duke@0 2773 }
duke@0 2774
duke@0 2775
duke@0 2776 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
duke@0 2777 ciMethod* method = op->profiled_method();
duke@0 2778 int bci = op->profiled_bci();
duke@0 2779
duke@0 2780 // Update counter for all call types
duke@0 2781 ciMethodData* md = method->method_data();
duke@0 2782 if (md == NULL) {
duke@0 2783 bailout("out of memory building methodDataOop");
duke@0 2784 return;
duke@0 2785 }
duke@0 2786 ciProfileData* data = md->bci_to_data(bci);
duke@0 2787 assert(data->is_CounterData(), "need CounterData for calls");
duke@0 2788 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
duke@0 2789 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
duke@0 2790 Register mdo = op->mdo()->as_register();
duke@0 2791 Register tmp1 = op->tmp1()->as_register();
duke@0 2792 jobject2reg(md->encoding(), mdo);
duke@0 2793 int mdo_offset_bias = 0;
duke@0 2794 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
duke@0 2795 data->size_in_bytes())) {
duke@0 2796 // The offset is large so bias the mdo by the base of the slot so
duke@0 2797 // that the ld can use simm13s to reference the slots of the data
duke@0 2798 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
duke@0 2799 __ set(mdo_offset_bias, O7);
duke@0 2800 __ add(mdo, O7, mdo);
duke@0 2801 }
duke@0 2802
duke@0 2803 Address counter_addr(mdo, 0, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
duke@0 2804 __ lduw(counter_addr, tmp1);
duke@0 2805 __ add(tmp1, DataLayout::counter_increment, tmp1);
duke@0 2806 __ stw(tmp1, counter_addr);
duke@0 2807 Bytecodes::Code bc = method->java_code_at_bci(bci);
duke@0 2808 // Perform additional virtual call profiling for invokevirtual and
duke@0 2809 // invokeinterface bytecodes
duke@0 2810 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
duke@0 2811 Tier1ProfileVirtualCalls) {
duke@0 2812 assert(op->recv()->is_single_cpu(), "recv must be allocated");
duke@0 2813 Register recv = op->recv()->as_register();
duke@0 2814 assert_different_registers(mdo, tmp1, recv);
duke@0 2815 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
duke@0 2816 ciKlass* known_klass = op->known_holder();
duke@0 2817 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) {
duke@0 2818 // We know the type that will be seen at this call site; we can
duke@0 2819 // statically update the methodDataOop rather than needing to do
duke@0 2820 // dynamic tests on the receiver type
duke@0 2821
duke@0 2822 // NOTE: we should probably put a lock around this search to
duke@0 2823 // avoid collisions by concurrent compilations
duke@0 2824 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
duke@0 2825 uint i;
duke@0 2826 for (i = 0; i < VirtualCallData::row_limit(); i++) {
duke@0 2827 ciKlass* receiver = vc_data->receiver(i);
duke@0 2828 if (known_klass->equals(receiver)) {
duke@0 2829 Address data_addr(mdo, 0, md->byte_offset_of_slot(data,
duke@0 2830 VirtualCallData::receiver_count_offset(i)) -
duke@0 2831 mdo_offset_bias);
duke@0 2832 __ lduw(data_addr, tmp1);
duke@0 2833 __ add(tmp1, DataLayout::counter_increment, tmp1);
duke@0 2834 __ stw(tmp1, data_addr);
duke@0 2835 return;
duke@0 2836 }
duke@0 2837 }
duke@0 2838
duke@0 2839 // Receiver type not found in profile data; select an empty slot
duke@0 2840
duke@0 2841 // Note that this is less efficient than it should be because it
duke@0 2842 // always does a write to the receiver part of the
duke@0 2843 // VirtualCallData rather than just the first time
duke@0 2844 for (i = 0; i < VirtualCallData::row_limit(); i++) {
duke@0 2845 ciKlass* receiver = vc_data->receiver(i);
duke@0 2846 if (receiver == NULL) {
duke@0 2847 Address recv_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
duke@0 2848 mdo_offset_bias);
duke@0 2849 jobject2reg(known_klass->encoding(), tmp1);
duke@0 2850 __ st_ptr(tmp1, recv_addr);
duke@0 2851 Address data_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
duke@0 2852 mdo_offset_bias);
duke@0 2853 __ lduw(data_addr, tmp1);
duke@0 2854 __ add(tmp1, DataLayout::counter_increment, tmp1);
duke@0 2855 __ stw(tmp1, data_addr);
duke@0 2856 return;
duke@0 2857 }
duke@0 2858 }
duke@0 2859 } else {
duke@0 2860 load(Address(recv, 0, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
duke@0 2861 Label update_done;
duke@0 2862 uint i;
duke@0 2863 for (i = 0; i < VirtualCallData::row_limit(); i++) {
duke@0 2864 Label next_test;
duke@0 2865 // See if the receiver is receiver[n].
duke@0 2866 Address receiver_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
duke@0 2867 mdo_offset_bias);
duke@0 2868 __ ld_ptr(receiver_addr, tmp1);
duke@0 2869 __ verify_oop(tmp1);
duke@0 2870 __ cmp(recv, tmp1);
duke@0 2871 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
duke@0 2872 __ delayed()->nop();
duke@0 2873 Address data_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
duke@0 2874 mdo_offset_bias);
duke@0 2875 __ lduw(data_addr, tmp1);
duke@0 2876 __ add(tmp1, DataLayout::counter_increment, tmp1);
duke@0 2877 __ stw(tmp1, data_addr);
duke@0 2878 __ br(Assembler::always, false, Assembler::pt, update_done);
duke@0 2879 __ delayed()->nop();
duke@0 2880 __ bind(next_test);
duke@0 2881 }
duke@0 2882
duke@0 2883 // Didn't find receiver; find next empty slot and fill it in
duke@0 2884 for (i = 0; i < VirtualCallData::row_limit(); i++) {
duke@0 2885 Label next_test;
duke@0 2886 Address recv_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
duke@0 2887 mdo_offset_bias);
duke@0 2888 load(recv_addr, tmp1, T_OBJECT);
duke@0 2889 __ tst(tmp1);
duke@0 2890 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
duke@0 2891 __ delayed()->nop();
duke@0 2892 __ st_ptr(recv, recv_addr);
duke@0 2893 __ set(DataLayout::counter_increment, tmp1);
duke@0 2894 __ st_ptr(tmp1, Address(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
duke@0 2895 mdo_offset_bias));
duke@0 2896 if (i < (VirtualCallData::row_limit() - 1)) {
duke@0 2897 __ br(Assembler::always, false, Assembler::pt, update_done);
duke@0 2898 __ delayed()->nop();
duke@0 2899 }
duke@0 2900 __ bind(next_test);
duke@0 2901 }
duke@0 2902
duke@0 2903 __ bind(update_done);
duke@0 2904 }
duke@0 2905 }
duke@0 2906 }
duke@0 2907
duke@0 2908
duke@0 2909 void LIR_Assembler::align_backward_branch_target() {
duke@0 2910 __ align(16);
duke@0 2911 }
duke@0 2912
duke@0 2913
duke@0 2914 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
duke@0 2915 // make sure we are expecting a delay
duke@0 2916 // this has the side effect of clearing the delay state
duke@0 2917 // so we can use _masm instead of _masm->delayed() to do the
duke@0 2918 // code generation.
duke@0 2919 __ delayed();
duke@0 2920
duke@0 2921 // make sure we only emit one instruction
duke@0 2922 int offset = code_offset();
duke@0 2923 op->delay_op()->emit_code(this);
duke@0 2924 #ifdef ASSERT
duke@0 2925 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
duke@0 2926 op->delay_op()->print();
duke@0 2927 }
duke@0 2928 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
duke@0 2929 "only one instruction can go in a delay slot");
duke@0 2930 #endif
duke@0 2931
duke@0 2932 // we may also be emitting the call info for the instruction
duke@0 2933 // which we are the delay slot of.
duke@0 2934 CodeEmitInfo * call_info = op->call_info();
duke@0 2935 if (call_info) {
duke@0 2936 add_call_info(code_offset(), call_info);
duke@0 2937 }
duke@0 2938
duke@0 2939 if (VerifyStackAtCalls) {
duke@0 2940 _masm->sub(FP, SP, O7);
duke@0 2941 _masm->cmp(O7, initial_frame_size_in_bytes());
duke@0 2942 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
duke@0 2943 }
duke@0 2944 }
duke@0 2945
duke@0 2946
duke@0 2947 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
duke@0 2948 assert(left->is_register(), "can only handle registers");
duke@0 2949
duke@0 2950 if (left->is_single_cpu()) {
duke@0 2951 __ neg(left->as_register(), dest->as_register());
duke@0 2952 } else if (left->is_single_fpu()) {
duke@0 2953 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
duke@0 2954 } else if (left->is_double_fpu()) {
duke@0 2955 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
duke@0 2956 } else {
duke@0 2957 assert (left->is_double_cpu(), "Must be a long");
duke@0 2958 Register Rlow = left->as_register_lo();
duke@0 2959 Register Rhi = left->as_register_hi();
duke@0 2960 #ifdef _LP64
duke@0 2961 __ sub(G0, Rlow, dest->as_register_lo());
duke@0 2962 #else
duke@0 2963 __ subcc(G0, Rlow, dest->as_register_lo());
duke@0 2964 __ subc (G0, Rhi, dest->as_register_hi());
duke@0 2965 #endif
duke@0 2966 }
duke@0 2967 }
duke@0 2968
duke@0 2969
duke@0 2970 void LIR_Assembler::fxch(int i) {
duke@0 2971 Unimplemented();
duke@0 2972 }
duke@0 2973
duke@0 2974 void LIR_Assembler::fld(int i) {
duke@0 2975 Unimplemented();
duke@0 2976 }
duke@0 2977
duke@0 2978 void LIR_Assembler::ffree(int i) {
duke@0 2979 Unimplemented();
duke@0 2980 }
duke@0 2981
duke@0 2982 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
duke@0 2983 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
duke@0 2984
duke@0 2985 // if tmp is invalid, then the function being called doesn't destroy the thread
duke@0 2986 if (tmp->is_valid()) {
duke@0 2987 __ save_thread(tmp->as_register());
duke@0 2988 }
duke@0 2989 __ call(dest, relocInfo::runtime_call_type);
duke@0 2990 __ delayed()->nop();
duke@0 2991 if (info != NULL) {
duke@0 2992 add_call_info_here(info);
duke@0 2993 }
duke@0 2994 if (tmp->is_valid()) {
duke@0 2995 __ restore_thread(tmp->as_register());
duke@0 2996 }
duke@0 2997
duke@0 2998 #ifdef ASSERT
duke@0 2999 __ verify_thread();
duke@0 3000 #endif // ASSERT
duke@0 3001 }
duke@0 3002
duke@0 3003
duke@0 3004 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
duke@0 3005 #ifdef _LP64
duke@0 3006 ShouldNotReachHere();
duke@0 3007 #endif
duke@0 3008
duke@0 3009 NEEDS_CLEANUP;
duke@0 3010 if (type == T_LONG) {
duke@0 3011 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
duke@0 3012
duke@0 3013 // (extended to allow indexed as well as constant displaced for JSR-166)
duke@0 3014 Register idx = noreg; // contains either constant offset or index
duke@0 3015
duke@0 3016 int disp = mem_addr->disp();
duke@0 3017 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
duke@0 3018 if (!Assembler::is_simm13(disp)) {
duke@0 3019 idx = O7;
duke@0 3020 __ set(disp, idx);
duke@0 3021 }
duke@0 3022 } else {
duke@0 3023 assert(disp == 0, "not both indexed and disp");
duke@0 3024 idx = mem_addr->index()->as_register();
duke@0 3025 }
duke@0 3026
duke@0 3027 int null_check_offset = -1;
duke@0 3028
duke@0 3029 Register base = mem_addr->base()->as_register();
duke@0 3030 if (src->is_register() && dest->is_address()) {
duke@0 3031 // G4 is high half, G5 is low half
duke@0 3032 if (VM_Version::v9_instructions_work()) {
duke@0 3033 // clear the top bits of G5, and scale up G4
duke@0 3034 __ srl (src->as_register_lo(), 0, G5);
duke@0 3035 __ sllx(src->as_register_hi(), 32, G4);
duke@0 3036 // combine the two halves into the 64 bits of G4
duke@0 3037 __ or3(G4, G5, G4);
duke@0 3038 null_check_offset = __ offset();
duke@0 3039 if (idx == noreg) {
duke@0 3040 __ stx(G4, base, disp);
duke@0 3041 } else {
duke@0 3042 __ stx(G4, base, idx);
duke@0 3043 }
duke@0 3044 } else {
duke@0 3045 __ mov (src->as_register_hi(), G4);
duke@0 3046 __ mov (src->as_register_lo(), G5);
duke@0 3047 null_check_offset = __ offset();
duke@0 3048 if (idx == noreg) {
duke@0 3049 __ std(G4, base, disp);
duke@0 3050 } else {
duke@0 3051 __ std(G4, base, idx);
duke@0 3052 }
duke@0 3053 }
duke@0 3054 } else if (src->is_address() && dest->is_register()) {
duke@0 3055 null_check_offset = __ offset();
duke@0 3056 if (VM_Version::v9_instructions_work()) {
duke@0 3057 if (idx == noreg) {
duke@0 3058 __ ldx(base, disp, G5);
duke@0 3059 } else {
duke@0 3060 __ ldx(base, idx, G5);
duke@0 3061 }
duke@0 3062 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
duke@0 3063 __ mov (G5, dest->as_register_lo()); // copy low half into lo
duke@0 3064 } else {
duke@0 3065 if (idx == noreg) {
duke@0 3066 __ ldd(base, disp, G4);
duke@0 3067 } else {
duke@0 3068 __ ldd(base, idx, G4);
duke@0 3069 }
duke@0 3070 // G4 is high half, G5 is low half
duke@0 3071 __ mov (G4, dest->as_register_hi());
duke@0 3072 __ mov (G5, dest->as_register_lo());
duke@0 3073 }
duke@0 3074 } else {
duke@0 3075 Unimplemented();
duke@0 3076 }
duke@0 3077 if (info != NULL) {
duke@0 3078 add_debug_info_for_null_check(null_check_offset, info);
duke@0 3079 }
duke@0 3080
duke@0 3081 } else {
duke@0 3082 // use normal move for all other volatiles since they don't need
duke@0 3083 // special handling to remain atomic.
duke@0 3084 move_op(src, dest, type, lir_patch_none, info, false, false);
duke@0 3085 }
duke@0 3086 }
duke@0 3087
duke@0 3088 void LIR_Assembler::membar() {
duke@0 3089 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
duke@0 3090 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
duke@0 3091 }
duke@0 3092
duke@0 3093 void LIR_Assembler::membar_acquire() {
duke@0 3094 // no-op on TSO
duke@0 3095 }
duke@0 3096
duke@0 3097 void LIR_Assembler::membar_release() {
duke@0 3098 // no-op on TSO
duke@0 3099 }
duke@0 3100
duke@0 3101 // Macro to Pack two sequential registers containing 32 bit values
duke@0 3102 // into a single 64 bit register.
duke@0 3103 // rs and rs->successor() are packed into rd
duke@0 3104 // rd and rs may be the same register.
duke@0 3105 // Note: rs and rs->successor() are destroyed.
duke@0 3106 void LIR_Assembler::pack64( Register rs, Register rd ) {
duke@0 3107 __ sllx(rs, 32, rs);
duke@0 3108 __ srl(rs->successor(), 0, rs->successor());
duke@0 3109 __ or3(rs, rs->successor(), rd);
duke@0 3110 }
duke@0 3111
duke@0 3112 // Macro to unpack a 64 bit value in a register into
duke@0 3113 // two sequential registers.
duke@0 3114 // rd is unpacked into rd and rd->successor()
duke@0 3115 void LIR_Assembler::unpack64( Register rd ) {
duke@0 3116 __ mov(rd, rd->successor());
duke@0 3117 __ srax(rd, 32, rd);
duke@0 3118 __ sra(rd->successor(), 0, rd->successor());
duke@0 3119 }
duke@0 3120
duke@0 3121
duke@0 3122 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
duke@0 3123 LIR_Address* addr = addr_opr->as_address_ptr();
duke@0 3124 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
duke@0 3125 __ add(addr->base()->as_register(), addr->disp(), dest->as_register());
duke@0 3126 }
duke@0 3127
duke@0 3128
duke@0 3129 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
duke@0 3130 assert(result_reg->is_register(), "check");
duke@0 3131 __ mov(G2_thread, result_reg->as_register());
duke@0 3132 }
duke@0 3133
duke@0 3134
duke@0 3135 void LIR_Assembler::peephole(LIR_List* lir) {
duke@0 3136 LIR_OpList* inst = lir->instructions_list();
duke@0 3137 for (int i = 0; i < inst->length(); i++) {
duke@0 3138 LIR_Op* op = inst->at(i);
duke@0 3139 switch (op->code()) {
duke@0 3140 case lir_cond_float_branch:
duke@0 3141 case lir_branch: {
duke@0 3142 LIR_OpBranch* branch = op->as_OpBranch();
duke@0 3143 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
duke@0 3144 LIR_Op* delay_op = NULL;
duke@0 3145 // we'd like to be able to pull following instructions into
duke@0 3146 // this slot but we don't know enough to do it safely yet so
duke@0 3147 // only optimize block to block control flow.
duke@0 3148 if (LIRFillDelaySlots && branch->block()) {
duke@0 3149 LIR_Op* prev = inst->at(i - 1);
duke@0 3150 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
duke@0 3151 // swap previous instruction into delay slot
duke@0 3152 inst->at_put(i - 1, op);
duke@0 3153 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
duke@0 3154 #ifndef PRODUCT
duke@0 3155 if (LIRTracePeephole) {
duke@0 3156 tty->print_cr("delayed");
duke@0 3157 inst->at(i - 1)->print();
duke@0 3158 inst->at(i)->print();
duke@0 3159 }
duke@0 3160 #endif
duke@0 3161 continue;
duke@0 3162 }
duke@0 3163 }
duke@0 3164
duke@0 3165 if (!delay_op) {
duke@0 3166 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
duke@0 3167 }
duke@0 3168 inst->insert_before(i + 1, delay_op);
duke@0 3169 break;
duke@0 3170 }
duke@0 3171 case lir_static_call:
duke@0 3172 case lir_virtual_call:
duke@0 3173 case lir_icvirtual_call:
duke@0 3174 case lir_optvirtual_call: {
duke@0 3175 LIR_Op* delay_op = NULL;
duke@0 3176 LIR_Op* prev = inst->at(i - 1);
duke@0 3177 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
duke@0 3178 (op->code() != lir_virtual_call ||
duke@0 3179 !prev->result_opr()->is_single_cpu() ||
duke@0 3180 prev->result_opr()->as_register() != O0) &&
duke@0 3181 LIR_Assembler::is_single_instruction(prev)) {
duke@0 3182 // Only moves without info can be put into the delay slot.
duke@0 3183 // Also don't allow the setup of the receiver in the delay
duke@0 3184 // slot for vtable calls.
duke@0 3185 inst->at_put(i - 1, op);
duke@0 3186 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
duke@0 3187 #ifndef PRODUCT
duke@0 3188 if (LIRTracePeephole) {
duke@0 3189 tty->print_cr("delayed");
duke@0 3190 inst->at(i - 1)->print();
duke@0 3191 inst->at(i)->print();
duke@0 3192 }
duke@0 3193 #endif
duke@0 3194 continue;
duke@0 3195 }
duke@0 3196
duke@0 3197 if (!delay_op) {
duke@0 3198 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
duke@0 3199 inst->insert_before(i + 1, delay_op);
duke@0 3200 }
duke@0 3201 break;
duke@0 3202 }
duke@0 3203 }
duke@0 3204 }
duke@0 3205 }
duke@0 3206
duke@0 3207
duke@0 3208
duke@0 3209
duke@0 3210 #undef __