comparison src/share/vm/c1/c1_LIRAssembler.hpp @ 0:a61af66fc99e

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author duke
date Sat, 01 Dec 2007 00:00:00 +0000
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children dc7f315e41f7 37f87013dfd8
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1 /*
2 * Copyright 2000-2006 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class Compilation;
26 class ScopeValue;
27
28 class LIR_Assembler: public CompilationResourceObj {
29 private:
30 C1_MacroAssembler* _masm;
31 CodeStubList* _slow_case_stubs;
32
33 Compilation* _compilation;
34 FrameMap* _frame_map;
35 BlockBegin* _current_block;
36
37 Instruction* _pending_non_safepoint;
38 int _pending_non_safepoint_offset;
39
40 #ifdef ASSERT
41 BlockList _branch_target_blocks;
42 void check_no_unbound_labels();
43 #endif
44
45 FrameMap* frame_map() const { return _frame_map; }
46
47 void set_current_block(BlockBegin* b) { _current_block = b; }
48 BlockBegin* current_block() const { return _current_block; }
49
50 // non-safepoint debug info management
51 void flush_debug_info(int before_pc_offset) {
52 if (_pending_non_safepoint != NULL) {
53 if (_pending_non_safepoint_offset < before_pc_offset)
54 record_non_safepoint_debug_info();
55 _pending_non_safepoint = NULL;
56 }
57 }
58 void process_debug_info(LIR_Op* op);
59 void record_non_safepoint_debug_info();
60
61 // unified bailout support
62 void bailout(const char* msg) const { compilation()->bailout(msg); }
63 bool bailed_out() const { return compilation()->bailed_out(); }
64
65 // code emission patterns and accessors
66 void check_codespace();
67 bool needs_icache(ciMethod* method) const;
68
69 // returns offset of icache check
70 int check_icache();
71
72 void jobject2reg(jobject o, Register reg);
73 void jobject2reg_with_patching(Register reg, CodeEmitInfo* info);
74
75 void emit_stubs(CodeStubList* stub_list);
76
77 // addresses
78 static Address as_Address(LIR_Address* addr);
79 static Address as_Address_lo(LIR_Address* addr);
80 static Address as_Address_hi(LIR_Address* addr);
81
82 // debug information
83 void add_call_info(int pc_offset, CodeEmitInfo* cinfo);
84 void add_debug_info_for_branch(CodeEmitInfo* info);
85 void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo);
86 void add_debug_info_for_div0_here(CodeEmitInfo* info);
87 void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);
88 void add_debug_info_for_null_check_here(CodeEmitInfo* info);
89
90 void set_24bit_FPU();
91 void reset_FPU();
92 void fpop();
93 void fxch(int i);
94 void fld(int i);
95 void ffree(int i);
96
97 void breakpoint();
98 void push(LIR_Opr opr);
99 void pop(LIR_Opr opr);
100
101 // patching
102 void append_patching_stub(PatchingStub* stub);
103 void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info);
104
105 void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op);
106
107 public:
108 LIR_Assembler(Compilation* c);
109 ~LIR_Assembler();
110 C1_MacroAssembler* masm() const { return _masm; }
111 Compilation* compilation() const { return _compilation; }
112 ciMethod* method() const { return compilation()->method(); }
113
114 CodeOffsets* offsets() const { return _compilation->offsets(); }
115 int code_offset() const;
116 address pc() const;
117
118 int initial_frame_size_in_bytes();
119
120 // test for constants which can be encoded directly in instructions
121 static bool is_small_constant(LIR_Opr opr);
122
123 static LIR_Opr receiverOpr();
124 static LIR_Opr incomingReceiverOpr();
125 static LIR_Opr osrBufferPointer();
126
127 // stubs
128 void emit_slow_case_stubs();
129 void emit_static_call_stub();
130 void emit_code_stub(CodeStub* op);
131 void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); }
132
133 // code patterns
134 void emit_exception_handler();
135 void emit_exception_entries(ExceptionInfoList* info_list);
136 void emit_deopt_handler();
137
138 void emit_code(BlockList* hir);
139 void emit_block(BlockBegin* block);
140 void emit_lir_list(LIR_List* list);
141
142 // any last minute peephole optimizations are performed here. In
143 // particular sparc uses this for delay slot filling.
144 void peephole(LIR_List* list);
145
146 void emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info);
147
148 void return_op(LIR_Opr result);
149
150 // returns offset of poll instruction
151 int safepoint_poll(LIR_Opr result, CodeEmitInfo* info);
152
153 void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info);
154 void const2stack(LIR_Opr src, LIR_Opr dest);
155 void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info);
156 void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack);
157 void reg2reg (LIR_Opr src, LIR_Opr dest);
158 void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned);
159 void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type);
160 void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type);
161 void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type,
162 LIR_PatchCode patch_code = lir_patch_none,
163 CodeEmitInfo* info = NULL, bool unaligned = false);
164
165 void prefetchr (LIR_Opr src);
166 void prefetchw (LIR_Opr src);
167
168 void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp);
169 void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest);
170
171 void move_regs(Register from_reg, Register to_reg);
172 void swap_reg(Register a, Register b);
173
174 void emit_op0(LIR_Op0* op);
175 void emit_op1(LIR_Op1* op);
176 void emit_op2(LIR_Op2* op);
177 void emit_op3(LIR_Op3* op);
178 void emit_opBranch(LIR_OpBranch* op);
179 void emit_opLabel(LIR_OpLabel* op);
180 void emit_arraycopy(LIR_OpArrayCopy* op);
181 void emit_opConvert(LIR_OpConvert* op);
182 void emit_alloc_obj(LIR_OpAllocObj* op);
183 void emit_alloc_array(LIR_OpAllocArray* op);
184 void emit_opTypeCheck(LIR_OpTypeCheck* op);
185 void emit_compare_and_swap(LIR_OpCompareAndSwap* op);
186 void emit_lock(LIR_OpLock* op);
187 void emit_call(LIR_OpJavaCall* op);
188 void emit_rtcall(LIR_OpRTCall* op);
189 void emit_profile_call(LIR_OpProfileCall* op);
190 void emit_delay(LIR_OpDelay* op);
191
192 void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack);
193 void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info);
194 void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op);
195
196 void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
197
198 void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack);
199 void move_op(LIR_Opr src, LIR_Opr result, BasicType type,
200 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned);
201 void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);
202 void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions
203 void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op);
204 void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result);
205
206 void ic_call(address destination, CodeEmitInfo* info);
207 void vtable_call(int vtable_offset, CodeEmitInfo* info);
208 void call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info);
209
210 void osr_entry();
211
212 void build_frame();
213
214 void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind);
215 void monitor_address(int monitor_ix, LIR_Opr dst);
216
217 void align_backward_branch_target();
218 void align_call(LIR_Code code);
219
220 void negate(LIR_Opr left, LIR_Opr dest);
221 void leal(LIR_Opr left, LIR_Opr dest);
222
223 void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info);
224
225 void membar();
226 void membar_acquire();
227 void membar_release();
228 void get_thread(LIR_Opr result);
229
230 void verify_oop_map(CodeEmitInfo* info);
231
232 #include "incls/_c1_LIRAssembler_pd.hpp.incl"
233 };