changeset 12319:f5689e544d44

8169901: AArch64: CompareAndExchange intrinsics clobber address register Reviewed-by: aph
author rkennke
date Fri, 18 Nov 2016 19:04:48 +0000
parents 0be832746ebe
children 3f551de87e59
files src/cpu/aarch64/vm/aarch64.ad src/cpu/aarch64/vm/cas.m4
diffstat 2 files changed, 56 insertions(+), 16 deletions(-) [+]
line wrap: on
line diff
--- a/src/cpu/aarch64/vm/aarch64.ad	Fri Nov 18 18:46:08 2016 +0300
+++ b/src/cpu/aarch64/vm/aarch64.ad	Fri Nov 18 19:04:48 2016 +0000
@@ -9646,6 +9646,10 @@
 
 
 // ---------------------------------------------------------------------
+
+
+// BEGIN This section of the file is automatically generated. Do not edit --------------
+
 // Sundry CAS operations.  Note that release is always true,
 // regardless of the memory ordering of the CAS.  This is because we
 // need the volatile case to be sequentially consistent but there is
@@ -9656,10 +9660,11 @@
 // This section is generated from aarch64_ad_cas.m4
 
 
-instruct compareAndExchangeB(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
+
+instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
   ins_cost(2 * VOLATILE_REF_COST);
-  effect(KILL cr);
+  effect(TEMP_DEF res, KILL cr);
   format %{
     "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
   %}
@@ -9673,10 +9678,10 @@
   ins_pipe(pipe_slow);
 %}
 
-instruct compareAndExchangeS(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
+instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
   ins_cost(2 * VOLATILE_REF_COST);
-  effect(KILL cr);
+  effect(TEMP_DEF res, KILL cr);
   format %{
     "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
   %}
@@ -9690,10 +9695,10 @@
   ins_pipe(pipe_slow);
 %}
 
-instruct compareAndExchangeI(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
+instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
   match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
   ins_cost(2 * VOLATILE_REF_COST);
-  effect(KILL cr);
+  effect(TEMP_DEF res, KILL cr);
   format %{
     "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
   %}
@@ -9705,10 +9710,10 @@
   ins_pipe(pipe_slow);
 %}
 
-instruct compareAndExchangeL(iRegL_R0 res, indirect mem, iRegL_R2 oldval, iRegL_R3 newval, rFlagsReg cr) %{
+instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
   match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
   ins_cost(2 * VOLATILE_REF_COST);
-  effect(KILL cr);
+  effect(TEMP_DEF res, KILL cr);
   format %{
     "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
   %}
@@ -9720,10 +9725,10 @@
   ins_pipe(pipe_slow);
 %}
 
-instruct compareAndExchangeN(iRegN_R0 res, indirect mem, iRegN_R2 oldval, iRegN_R3 newval, rFlagsReg cr) %{
+instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
   match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
   ins_cost(2 * VOLATILE_REF_COST);
-  effect(KILL cr);
+  effect(TEMP_DEF res, KILL cr);
   format %{
     "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
   %}
@@ -9735,10 +9740,10 @@
   ins_pipe(pipe_slow);
 %}
 
-instruct compareAndExchangeP(iRegP_R0 res, indirect mem, iRegP_R2 oldval, iRegP_R3 newval, rFlagsReg cr) %{
+instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
   match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
   ins_cost(2 * VOLATILE_REF_COST);
-  effect(KILL cr);
+  effect(TEMP_DEF res, KILL cr);
   format %{
     "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
   %}
@@ -9853,6 +9858,8 @@
   %}
   ins_pipe(pipe_slow);
 %}
+
+// END This section of the file is automatically generated. Do not edit --------------
 // ---------------------------------------------------------------------
 
 instruct get_and_setI(indirect mem, iRegINoSp newv, iRegI prev) %{
--- a/src/cpu/aarch64/vm/cas.m4	Fri Nov 18 18:46:08 2016 +0300
+++ b/src/cpu/aarch64/vm/cas.m4	Fri Nov 18 19:04:48 2016 +0000
@@ -1,3 +1,31 @@
+dnl Copyright (c) 2016, Red Hat Inc. All rights reserved.
+dnl DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+dnl
+dnl This code is free software; you can redistribute it and/or modify it
+dnl under the terms of the GNU General Public License version 2 only, as
+dnl published by the Free Software Foundation.
+dnl
+dnl This code is distributed in the hope that it will be useful, but WITHOUT
+dnl ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+dnl FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+dnl version 2 for more details (a copy is included in the LICENSE file that
+dnl accompanied this code).
+dnl
+dnl You should have received a copy of the GNU General Public License version
+dnl 2 along with this work; if not, write to the Free Software Foundation,
+dnl Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+dnl
+dnl Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+dnl or visit www.oracle.com if you need additional information or have any
+dnl questions.
+dnl
+dnl 
+dnl Process this file with m4 cas.m4 to generate the CAE and wCAS
+dnl instructions used in aarch64.ad.
+dnl
+
+// BEGIN This section of the file is automatically generated. Do not edit --------------
+
 // Sundry CAS operations.  Note that release is always true,
 // regardless of the memory ordering of the CAS.  This is because we
 // need the volatile case to be sequentially consistent but there is
@@ -5,13 +33,16 @@
 // can't check the type of memory ordering here, so we always emit a
 // STLXR.
 
+// This section is generated from aarch64_ad_cas.m4
+
+
 define(`CAS_INSN',
 `
-instruct compareAndExchange$1$5(iReg$2_R0 res, indirect mem, iReg$2_R2 oldval, iReg$2_R3 newval, rFlagsReg cr) %{
+instruct compareAndExchange$1$5(iReg$2NoSp res, indirect mem, iReg$2 oldval, iReg$2 newval, rFlagsReg cr) %{
   match(Set res (CompareAndExchange$1 mem (Binary oldval newval)));
   ifelse($5,Acq,'  predicate(needs_acquiring_load_exclusive(n));
   ins_cost(VOLATILE_REF_COST);`,'  ins_cost(2 * VOLATILE_REF_COST);`)
-  effect(KILL cr);
+  effect(TEMP_DEF res, KILL cr);
   format %{
     "cmpxchg $res = $mem, $oldval, $newval\t# ($3, weak) if $mem == $oldval then $mem <-- $newval"
   %}
@@ -24,11 +55,11 @@
 %}')dnl
 define(`CAS_INSN4',
 `
-instruct compareAndExchange$1$7(iReg$2_R0 res, indirect mem, iReg$2_R2 oldval, iReg$2_R3 newval, rFlagsReg cr) %{
+instruct compareAndExchange$1$7(iReg$2NoSp res, indirect mem, iReg$2 oldval, iReg$2 newval, rFlagsReg cr) %{
   match(Set res (CompareAndExchange$1 mem (Binary oldval newval)));
   ifelse($7,Acq,'  predicate(needs_acquiring_load_exclusive(n));
   ins_cost(VOLATILE_REF_COST);`,'  ins_cost(2 * VOLATILE_REF_COST);`)
-  effect(KILL cr);
+  effect(TEMP_DEF res, KILL cr);
   format %{
     "cmpxchg $res = $mem, $oldval, $newval\t# ($3, weak) if $mem == $oldval then $mem <-- $newval"
   %}
@@ -107,3 +138,5 @@
 dnl CAS_INSN3(N,N,narrow oop,word,Acq)
 dnl CAS_INSN3(P,P,ptr,xword,Acq)
 dnl
+
+// END This section of the file is automatically generated. Do not edit --------------