--- a/.hgtags	Wed Oct 31 11:45:04 2018 -0700
+++ b/.hgtags	Wed Oct 31 13:26:06 2018 -0700
@@ -519,3 +519,4 @@
 6f04692c7d5137ee34a6bd94c0c8a6c9219cb127 jdk-12+14
 f8626bcc169813a4b2a15880386b952719d1d6d1 jdk-12+15
 199658d1ef860cdc17055b4fd3e94b057f292fe9 jdk-12+16
+eefa65e142af305923d2adcd596fab9c639723a1 jdk-12+17

--- a/doc/building.html	Wed Oct 31 11:45:04 2018 -0700
+++ b/doc/building.html	Wed Oct 31 13:26:06 2018 -0700
@@ -707,7 +707,6 @@
 <p>Additional architectures might be supported by Debian/Ubuntu Ports.</p>
 <h3 id="building-for-armaarch64">Building for ARM/aarch64</h3>
 <p>A common cross-compilation target is the ARM CPU. When building for ARM, it is useful to set the ABI profile. A number of pre-defined ABI profiles are available using <code>--with-abi-profile</code>: arm-vfp-sflt, arm-vfp-hflt, arm-sflt, armv5-vfp-sflt, armv6-vfp-hflt. Note that soft-float ABIs are no longer properly supported by the JDK.</p>
-<p>The JDK contains two different ports for the aarch64 platform, one is the original aarch64 port from the <a href="http://openjdk.java.net/projects/aarch64-port">AArch64 Port Project</a> and one is a 64-bit version of the Oracle contributed ARM port. When targeting aarch64, by the default the original aarch64 port is used. To select the Oracle ARM 64 port, use <code>--with-cpu-port=arm64</code>. Also set the corresponding value (<code>aarch64</code> or <code>arm64</code>) to --with-abi-profile, to ensure a consistent build.</p>
 <h3 id="verifying-the-build">Verifying the Build</h3>
 <p>The build will end up in a directory named like <code>build/linux-arm-normal-server-release</code>.</p>
 <p>Inside this build output directory, the <code>images/jdk</code> will contain the newly built JDK, for your <em>target</em> system.</p>

--- a/doc/building.md	Wed Oct 31 11:45:04 2018 -0700
+++ b/doc/building.md	Wed Oct 31 13:26:06 2018 -0700
@@ -1080,14 +1080,6 @@
 armv5-vfp-sflt, armv6-vfp-hflt. Note that soft-float ABIs are no longer
 properly supported by the JDK.
 
-The JDK contains two different ports for the aarch64 platform, one is the
-original aarch64 port from the [AArch64 Port Project](
-http://openjdk.java.net/projects/aarch64-port) and one is a 64-bit version of
-the Oracle contributed ARM port. When targeting aarch64, by the default the
-original aarch64 port is used. To select the Oracle ARM 64 port, use
-`--with-cpu-port=arm64`. Also set the corresponding value (`aarch64` or
-`arm64`) to --with-abi-profile, to ensure a consistent build.
-
 ### Verifying the Build
 
 The build will end up in a directory named like

--- a/doc/testing.html	Wed Oct 31 11:45:04 2018 -0700
+++ b/doc/testing.html	Wed Oct 31 13:26:06 2018 -0700
@@ -18,12 +18,13 @@
 </header>
 <nav id="TOC">
 <ul>
-<li><a href="#using-the-run-test-framework">Using the run-test framework</a><ul>
+<li><a href="#using-make-test-the-run-test-framework">Using &quot;make test&quot; (the run-test framework)</a><ul>
 <li><a href="#configuration">Configuration</a></li>
 </ul></li>
 <li><a href="#test-selection">Test selection</a><ul>
 <li><a href="#jtreg">JTReg</a></li>
 <li><a href="#gtest">Gtest</a></li>
+<li><a href="#special-tests">Special tests</a></li>
 </ul></li>
 <li><a href="#test-results-and-summary">Test results and summary</a></li>
 <li><a href="#test-suite-control">Test suite control</a><ul>
@@ -32,22 +33,23 @@
 </ul></li>
 </ul>
 </nav>
-<h2 id="using-the-run-test-framework">Using the run-test framework</h2>
+<h2 id="using-make-test-the-run-test-framework">Using &quot;make test&quot; (the run-test framework)</h2>
 <p>This new way of running tests is developer-centric. It assumes that you have built a JDK locally and want to test it. Running common test targets is simple, and more complex ad-hoc combination of tests is possible. The user interface is forgiving, and clearly report errors it cannot resolve.</p>
-<p>The main target &quot;run-test&quot; uses the jdk-image as the tested product. There is also an alternate target &quot;exploded-run-test&quot; that uses the exploded image instead. Not all tests will run successfully on the exploded image, but using this target can greatly improve rebuild times for certain workflows.</p>
+<p>The main target <code>test</code> uses the jdk-image as the tested product. There is also an alternate target <code>exploded-test</code> that uses the exploded image instead. Not all tests will run successfully on the exploded image, but using this target can greatly improve rebuild times for certain workflows.</p>
+<p>Previously, <code>make test</code> was used invoke an old system for running test, and <code>make run-test</code> was used for the new test framework. For backward compatibility with scripts and muscle memory, <code>run-test</code> (and variants like <code>exploded-run-test</code> or <code>run-test-tier1</code>) are kept as aliases. The old system can still be accessed for some time using <code>cd test &amp;&amp; make</code>.</p>
 <p>Some example command-lines:</p>
-<pre><code>$ make run-test-tier1
-$ make run-test-jdk_lang JTREG=&quot;JOBS=8&quot;
-$ make run-test TEST=jdk_lang
-$ make run-test-only TEST=&quot;gtest:LogTagSet gtest:LogTagSetDescriptions&quot; GTEST=&quot;REPEAT=-1&quot;
-$ make run-test TEST=&quot;hotspot:hotspot_gc&quot; JTREG=&quot;JOBS=1;TIMEOUT=8;VM_OPTIONS=-XshowSettings -Xlog:gc+ref=debug&quot;
-$ make run-test TEST=&quot;jtreg:test/hotspot:hotspot_gc test/hotspot/jtreg/native_sanity/JniVersion.java&quot;
-$ make exploded-run-test TEST=tier2</code></pre>
+<pre><code>$ make test-tier1
+$ make test-jdk_lang JTREG=&quot;JOBS=8&quot;
+$ make test TEST=jdk_lang
+$ make test-only TEST=&quot;gtest:LogTagSet gtest:LogTagSetDescriptions&quot; GTEST=&quot;REPEAT=-1&quot;
+$ make test TEST=&quot;hotspot:hotspot_gc&quot; JTREG=&quot;JOBS=1;TIMEOUT=8;VM_OPTIONS=-XshowSettings -Xlog:gc+ref=debug&quot;
+$ make test TEST=&quot;jtreg:test/hotspot:hotspot_gc test/hotspot/jtreg/native_sanity/JniVersion.java&quot;
+$ make exploded-test TEST=tier2</code></pre>
 <h3 id="configuration">Configuration</h3>
 <p>To be able to run JTReg tests, <code>configure</code> needs to know where to find the JTReg test framework. If it is not picked up automatically by configure, use the <code>--with-jtreg=&lt;path to jtreg home&gt;</code> option to point to the JTReg framework. Note that this option should point to the JTReg home, i.e. the top directory, containing <code>lib/jtreg.jar</code> etc. (An alternative is to set the <code>JT_HOME</code> environment variable to point to the JTReg home before running <code>configure</code>.)</p>
 <h2 id="test-selection">Test selection</h2>
-<p>All functionality is available using the run-test make target. In this use case, the test or tests to be executed is controlled using the <code>TEST</code> variable. To speed up subsequent test runs with no source code changes, run-test-only can be used instead, which do not depend on the source and test image build.</p>
-<p>For some common top-level tests, direct make targets have been generated. This includes all JTReg test groups, the hotspot gtest, and custom tests (if present). This means that <code>make run-test-tier1</code> is equivalent to <code>make run-test TEST=&quot;tier1&quot;</code>, but the latter is more tab-completion friendly. For more complex test runs, the <code>run-test TEST=&quot;x&quot;</code> solution needs to be used.</p>
+<p>All functionality is available using the <code>test</code> make target. In this use case, the test or tests to be executed is controlled using the <code>TEST</code> variable. To speed up subsequent test runs with no source code changes, <code>test-only</code> can be used instead, which do not depend on the source and test image build.</p>
+<p>For some common top-level tests, direct make targets have been generated. This includes all JTReg test groups, the hotspot gtest, and custom tests (if present). This means that <code>make test-tier1</code> is equivalent to <code>make test TEST=&quot;tier1&quot;</code>, but the latter is more tab-completion friendly. For more complex test runs, the <code>test TEST=&quot;x&quot;</code> solution needs to be used.</p>
 <p>The test specifications given in <code>TEST</code> is parsed into fully qualified test descriptors, which clearly and unambigously show which tests will be run. As an example, <code>:tier1</code> will expand to <code>jtreg:$(TOPDIR)/test/hotspot/jtreg:tier1 jtreg:$(TOPDIR)/test/jdk:tier1 jtreg:$(TOPDIR)/test/langtools:tier1 jtreg:$(TOPDIR)/test/nashorn:tier1 jtreg:$(TOPDIR)/test/jaxp:tier1</code>. You can always submit a list of fully qualified test descriptors in the <code>TEST</code> variable if you want to shortcut the parser.</p>
 <h3 id="jtreg">JTReg</h3>
 <p>JTReg tests can be selected either by picking a JTReg test group, or a selection of files or directories containing JTReg tests.</p>
@@ -59,6 +61,14 @@
 <p>Since the Hotspot Gtest suite is so quick, the default is to run all tests. This is specified by just <code>gtest</code>, or as a fully qualified test descriptor <code>gtest:all</code>.</p>
 <p>If you want, you can single out an individual test or a group of tests, for instance <code>gtest:LogDecorations</code> or <code>gtest:LogDecorations.level_test_vm</code>. This can be particularly useful if you want to run a shaky test repeatedly.</p>
 <p>For Gtest, there is a separate test suite for each JVM variant. The JVM variant is defined by adding <code>/&lt;variant&gt;</code> to the test descriptor, e.g. <code>gtest:Log/client</code>. If you specify no variant, gtest will run once for each JVM variant present (e.g. server, client). So if you only have the server JVM present, then <code>gtest:all</code> will be equivalent to <code>gtest:all/server</code>.</p>
+<h3 id="special-tests">Special tests</h3>
+<p>A handful of odd tests that are not covered by any other testing framework are accessible using the <code>special:</code> test descriptor. Currently, this includes <code>hotspot-internal</code>, <code>failure-handler</code> and <code>make</code>.</p>
+<ul>
+<li><p>Hotspot legacy internal testing (run using <code>-XX:+ExecuteInternalVMTests</code>) is run using <code>special:hotspot-internal</code> or just <code>hotspot-internal</code> as test descriptor, and will only work on a debug JVM.</p></li>
+<li><p>Failure handler testing is run using <code>special:failure-handler</code> or just <code>failure-handler</code> as test descriptor.</p></li>
+<li><p>Tests for the build system, including both makefiles and related functionality, is run using <code>special:make</code> or just <code>make</code> as test descriptor. This is equivalent to <code>special:make:all</code>.</p>
+<p>A specific make test can be run by supplying it as argument, e.g. <code>special:make:idea</code>. As a special syntax, this can also be expressed as <code>make-idea</code>, which allows for command lines as <code>make test-make-idea</code>.</p></li>
+</ul>
 <h2 id="test-results-and-summary">Test results and summary</h2>
 <p>At the end of the test run, a summary of all tests run will be presented. This will have a consistent look, regardless of what test suites were used. This is a sample summary:</p>
 <pre><code>==============================
@@ -72,7 +82,7 @@
 TEST FAILURE</code></pre>
 <p>Tests where the number of TOTAL tests does not equal the number of PASSed tests will be considered a test failure. These are marked with the <code>&gt;&gt; ... &lt;&lt;</code> marker for easy identification.</p>
 <p>The classification of non-passed tests differs a bit between test suites. In the summary, ERROR is used as a catch-all for tests that neither passed nor are classified as failed by the framework. This might indicate test framework error, timeout or other problems.</p>
-<p>In case of test failures, <code>make run-test</code> will exit with a non-zero exit value.</p>
+<p>In case of test failures, <code>make test</code> will exit with a non-zero exit value.</p>
 <p>All tests have their result stored in <code>build/$BUILD/test-results/$TEST_ID</code>, where TEST_ID is a path-safe conversion from the fully qualified test descriptor, e.g. for <code>jtreg:jdk/test:tier1</code> the TEST_ID is <code>jtreg_jdk_test_tier1</code>. This path is also printed in the log at the end of the test run.</p>
 <p>Additional work data is stored in <code>build/$BUILD/test-support/$TEST_ID</code>. For some frameworks, this directory might contain information that is useful in determining the cause of a failed test.</p>
 <h2 id="test-suite-control">Test suite control</h2>

--- a/doc/testing.md	Wed Oct 31 11:45:04 2018 -0700
+++ b/doc/testing.md	Wed Oct 31 13:26:06 2018 -0700
@@ -1,26 +1,32 @@
 % Testing the JDK
 
-## Using the run-test framework
+## Using "make test" (the run-test framework)
 
 This new way of running tests is developer-centric. It assumes that you have
 built a JDK locally and want to test it. Running common test targets is simple,
 and more complex ad-hoc combination of tests is possible. The user interface is
 forgiving, and clearly report errors it cannot resolve.
 
-The main target "run-test" uses the jdk-image as the tested product. There is
-also an alternate target "exploded-run-test" that uses the exploded image
+The main target `test` uses the jdk-image as the tested product. There is
+also an alternate target `exploded-test` that uses the exploded image
 instead. Not all tests will run successfully on the exploded image, but using
 this target can greatly improve rebuild times for certain workflows.
 
+Previously, `make test` was used invoke an old system for running test, and
+`make run-test` was used for the new test framework. For backward compatibility
+with scripts and muscle memory, `run-test` (and variants like
+`exploded-run-test` or `run-test-tier1`) are kept as aliases. The old system
+can still be accessed for some time using `cd test && make`.
+
 Some example command-lines:
 
-    $ make run-test-tier1
-    $ make run-test-jdk_lang JTREG="JOBS=8"
-    $ make run-test TEST=jdk_lang
-    $ make run-test-only TEST="gtest:LogTagSet gtest:LogTagSetDescriptions" GTEST="REPEAT=-1"
-    $ make run-test TEST="hotspot:hotspot_gc" JTREG="JOBS=1;TIMEOUT=8;VM_OPTIONS=-XshowSettings -Xlog:gc+ref=debug"
-    $ make run-test TEST="jtreg:test/hotspot:hotspot_gc test/hotspot/jtreg/native_sanity/JniVersion.java"
-    $ make exploded-run-test TEST=tier2
+    $ make test-tier1
+    $ make test-jdk_lang JTREG="JOBS=8"
+    $ make test TEST=jdk_lang
+    $ make test-only TEST="gtest:LogTagSet gtest:LogTagSetDescriptions" GTEST="REPEAT=-1"
+    $ make test TEST="hotspot:hotspot_gc" JTREG="JOBS=1;TIMEOUT=8;VM_OPTIONS=-XshowSettings -Xlog:gc+ref=debug"
+    $ make test TEST="jtreg:test/hotspot:hotspot_gc test/hotspot/jtreg/native_sanity/JniVersion.java"
+    $ make exploded-test TEST=tier2
 
 ### Configuration
 
@@ -33,16 +39,16 @@
 
 ## Test selection
 
-All functionality is available using the run-test make target. In this use
-case, the test or tests to be executed is controlled using the `TEST` variable.
-To speed up subsequent test runs with no source code changes, run-test-only can
-be used instead, which do not depend on the source and test image build.
+All functionality is available using the `test` make target. In this use case,
+the test or tests to be executed is controlled using the `TEST` variable. To
+speed up subsequent test runs with no source code changes, `test-only` can be
+used instead, which do not depend on the source and test image build.
 
 For some common top-level tests, direct make targets have been generated. This
 includes all JTReg test groups, the hotspot gtest, and custom tests (if
-present). This means that `make run-test-tier1` is equivalent to `make run-test
+present). This means that `make test-tier1` is equivalent to `make test
 TEST="tier1"`, but the latter is more tab-completion friendly. For more complex
-test runs, the `run-test TEST="x"` solution needs to be used.
+test runs, the `test TEST="x"` solution needs to be used.
 
 The test specifications given in `TEST` is parsed into fully qualified test
 descriptors, which clearly and unambigously show which tests will be run. As an
@@ -98,6 +104,27 @@
 variant present (e.g. server, client). So if you only have the server JVM
 present, then `gtest:all` will be equivalent to `gtest:all/server`.
 
+### Special tests
+
+A handful of odd tests that are not covered by any other testing framework are
+accessible using the `special:` test descriptor. Currently, this includes
+`hotspot-internal`, `failure-handler` and `make`.
+
+  * Hotspot legacy internal testing (run using `-XX:+ExecuteInternalVMTests`)
+    is run using `special:hotspot-internal` or just `hotspot-internal` as test
+    descriptor, and will only work on a debug JVM.
+
+  * Failure handler testing is run using `special:failure-handler` or just
+    `failure-handler` as test descriptor.
+
+  * Tests for the build system, including both makefiles and related
+    functionality, is run using `special:make` or just `make` as test
+    descriptor. This is equivalent to `special:make:all`.
+
+    A specific make test can be run by supplying it as argument, e.g.
+    `special:make:idea`. As a special syntax, this can also be expressed as
+    `make-idea`, which allows for command lines as `make test-make-idea`.
+
 ## Test results and summary
 
 At the end of the test run, a summary of all tests run will be presented. This
@@ -123,7 +150,7 @@
 classified as failed by the framework. This might indicate test framework
 error, timeout or other problems.
 
-In case of test failures, `make run-test` will exit with a non-zero exit value.
+In case of test failures, `make test` will exit with a non-zero exit value.
 
 All tests have their result stored in `build/$BUILD/test-results/$TEST_ID`,
 where TEST_ID is a path-safe conversion from the fully qualified test

--- a/make/Docs.gmk	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/Docs.gmk	Wed Oct 31 13:26:06 2018 -0700
@@ -61,11 +61,11 @@
     $(SUPPORT_OUTPUTDIR)/rmic/* $(TOPDIR)/src/*/share/doc/stub)
 
 # URLs
-JAVADOC_BASE_URL := http://www.oracle.com/pls/topic/lookup?ctx=javase$(VERSION_NUMBER)&id=homepage
-BUG_SUBMIT_URL := http://bugreport.java.com/bugreport/
+JAVADOC_BASE_URL := https://docs.oracle.com/pls/topic/lookup?ctx=javase$(VERSION_NUMBER)&id=homepage
+BUG_SUBMIT_URL := https://bugreport.java.com/bugreport/
 COPYRIGHT_URL := {@docroot}/../legal/copyright.html
-LICENSE_URL := http://www.oracle.com/technetwork/java/javase/terms/license/java$(VERSION_NUMBER)speclicense.html
-REDISTRIBUTION_URL := http://www.oracle.com/technetwork/java/redist-137594.html
+LICENSE_URL := https://www.oracle.com/technetwork/java/javase/terms/license/java$(VERSION_NUMBER)speclicense.html
+REDISTRIBUTION_URL := https://www.oracle.com/technetwork/java/redist-137594.html
 
 # In order to get a specific ordering it's necessary to specify the total
 # ordering of tags as the tags are otherwise ordered in order of definition.

--- a/make/Help.gmk	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/Help.gmk	Wed Oct 31 13:26:06 2018 -0700
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2012, 2017, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2012, 2018, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -55,10 +55,10 @@
 	$(info $(_) make install           # Install the generated images locally)
 	$(info $(_) make reconfigure       # Rerun configure with the same arguments as last time)
 	$(info $(_) make help              # Give some help on using make)
-	$(info $(_) make test              # Run tests, default is all tests (see TEST below))
-	$(info $(_) make run-test-<test>   # Run test, e.g. run-test-tier1)
-	$(info $(_) make run-test TEST=<t> # Run test(s) given by TEST specification)
-	$(info $(_) make exploded-run-test TEST=<t> # Run test(s) on the exploded image instead of)
+	$(info $(_) make check             # Run basic testing (currently tier1))
+	$(info $(_) make test-<test>       # Run test, e.g. test-tier1)
+	$(info $(_) make test TEST=<t>     # Run test(s) given by TEST specification)
+	$(info $(_) make exploded-test TEST=<t> # Run test(s) on the exploded image instead of)
 	$(info $(_)                        # the full jdk image)
 	$(info )
 	$(info Targets for cleaning)
@@ -99,10 +99,12 @@
 	$(info $(_) TEST_JOBS=<n>          # Run <n> parallel test jobs)
 	$(info $(_) CONF_CHECK=<method>    # What to do if spec file is out of date)
 	$(info $(_)                        # method is 'auto', 'ignore' or 'fail' (default))
-	$(info $(_) make test TEST=<test>  # Only run the given test or tests, e.g.)
-	$(info $(_)                        # make test TEST="jdk_lang jdk_net")
-	$(info $(_) JTREG="OPT1=x;OPT2=y"  # Control the JTREG test harness for run-test)
-	$(info $(_) GTEST="OPT1=x;OPT2=y"  # Control the GTEST test harness for run-test)
+	$(info $(_) TEST="test1 ..."       # Use the given test descriptor(s) for testing, e.g.)
+	$(info $(_)                        # make test TEST="jdk_lang gtest:all")
+	$(info $(_) JTREG="OPT1=x;OPT2=y"  # Control the JTREG test harness)
+	$(info $(_) GTEST="OPT1=x;OPT2=y"  # Control the GTEST test harness)
+	$(info $(_) TEST_OPTS="OPT1=x;..." # Generic control of all test harnesses)
+	$(info $(_) TEST_VM_OPTS="ARG ..." # Same as setting TEST_OPTS to VM_OPTIONS="ARG ...")
 	$(info )
 	$(if $(all_confs), $(info Available configurations in $(build_dir):) $(foreach var,$(all_confs),$(info * $(var))),\
 	    $(info No configurations were found in $(build_dir).) $(info Run 'bash configure' to create a configuration.))

--- a/make/Main.gmk	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/Main.gmk	Wed Oct 31 13:26:06 2018 -0700
@@ -473,10 +473,10 @@
 #
 
 define DeclareRunTestRecipe
-  run-test-$1:
+  test-$1:
 	+($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f RunTests.gmk run-test TEST="$1")
 
-  exploded-run-test-$1:
+  exploded-test-$1:
 	+($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f RunTests.gmk run-test \
 	    TEST="$1" JDK_IMAGE_DIR=$(JDK_OUTPUTDIR))
 
@@ -484,8 +484,8 @@
 
 # ALL_NAMED_TESTS is defined in FindTests.gmk
 $(foreach t, $(ALL_NAMED_TESTS), $(eval $(call DeclareRunTestRecipe,$t)))
-ALL_TEST_TARGETS := $(addprefix run-test-, $(ALL_NAMED_TESTS))
-ALL_EXPLODED_TEST_TARGETS := $(addprefix exploded-run-test-, $(ALL_NAMED_TESTS))
+ALL_TEST_TARGETS := $(addprefix test-, $(ALL_NAMED_TESTS))
+ALL_EXPLODED_TEST_TARGETS := $(addprefix exploded-test-, $(ALL_NAMED_TESTS))
 
 ALL_TARGETS += $(ALL_TEST_TARGETS) $(ALL_EXPLODED_TEST_TARGETS)
 
@@ -520,13 +520,6 @@
 	+($(CD) $(TOPDIR)/make/test && $(MAKE) $(MAKE_ARGS) -f JtregGraalUnit.gmk \
 	     test-image-hotspot-jtreg-graal)
 
-run-test:
-	+($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f RunTests.gmk run-test TEST="$(TEST)")
-
-exploded-run-test:
-	+($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f RunTests.gmk run-test \
-	    TEST="$(TEST)" JDK_IMAGE_DIR=$(JDK_OUTPUTDIR))
-
 ifeq ($(BUILD_GTEST), true)
   test-image-hotspot-gtest:
 	+($(CD) $(TOPDIR)/make/hotspot/test && $(MAKE) $(MAKE_ARGS) -f GtestImage.gmk)
@@ -541,11 +534,6 @@
 	+($(CD) $(TOPDIR)/make/test && $(MAKE) $(MAKE_ARGS) \
 	    -f BuildFailureHandler.gmk build)
 
-  # Runs the tests for the failure handler jtreg extension
-  test-failure-handler:
-	+($(CD) $(TOPDIR)/make/test && $(MAKE) $(MAKE_ARGS) \
-	    -f BuildFailureHandler.gmk test)
-
   # Copies the failure handler jtreg extension into the test image
   test-image-failure-handler:
 	+($(CD) $(TOPDIR)/make/test && $(MAKE) $(MAKE_ARGS) \
@@ -556,40 +544,19 @@
     test-image-hotspot-jtreg-native build-test-jdk-jtreg-native \
     test-image-jdk-jtreg-native build-test-lib build-test-failure-handler \
     test-failure-handler test-image-failure-handler test-image-hotspot-gtest \
-    test-image-hotspot-jtreg-graal build-test-hotspot-jtreg-graal \
-    run-test exploded-run-test
+    test-image-hotspot-jtreg-graal build-test-hotspot-jtreg-graal
 
 ################################################################################
 # Run tests
 
-# Run tests specified by $(TEST), or the default test set.
 test:
-	$(call RunTests, $(TEST), $(JDK_IMAGE_DIR))
+	+($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f RunTests.gmk run-test TEST="$(TEST)")
 
-test-hotspot-jtreg:
-	$(call RunTests, "hotspot_all", $(JDK_IMAGE_DIR))
+exploded-test:
+	+($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f RunTests.gmk run-test \
+	    TEST="$(TEST)" JDK_IMAGE_DIR=$(JDK_OUTPUTDIR))
 
-test-hotspot-jtreg-native:
-	$(call RunTests, "hotspot_native_sanity", $(JDK_IMAGE_DIR))
-
-test-hotspot-internal:
-	$(call RunTests, "hotspot_internal", $(JDK_OUTPUTDIR))
-
-test-hotspot-gtest:
-	$(call RunTests, "hotspot_gtest", $(JDK_OUTPUTDIR))
-
-test-jdk-jtreg-native:
-	$(call RunTests, "jdk_native_sanity", $(JDK_IMAGE_DIR))
-
-test-make:
-	($(CD) $(TOPDIR)/test/make && $(MAKE) $(MAKE_ARGS) -f TestMake.gmk $(TEST_TARGET))
-
-test-compile-commands:
-	($(CD) $(TOPDIR)/test/make && $(MAKE) $(MAKE_ARGS) -f TestMake.gmk test-compile-commands)
-
-ALL_TARGETS += test test-hotspot-jtreg test-hotspot-jtreg-native \
-    test-hotspot-internal test-hotspot-gtest test-jdk-jtreg-native test-make \
-    test-compile-commands
+ALL_TARGETS += test exploded-test
 
 ################################################################################
 # Bundles
@@ -874,14 +841,18 @@
 
   docs-zip: docs-jdk
 
+  # Tests
   test: jdk-image test-image
 
-  run-test: jdk-image test-image
-  exploded-run-test: exploded-image test-image
+  exploded-test: exploded-image test-image
+
+  test-make: clean-test-make compile-commands
+
+  test-make-compile-commands: compile-commands
 
   # Declare dependency for all generated test targets
-  $(foreach t, $(ALL_TEST_TARGETS), $(eval $t: jdk-image test-image))
-  $(foreach t, $(ALL_EXPLODED_TEST_TARGETS), $(eval $t: exploded-image test-image))
+  $(foreach t, $(filter-out test-make%, $(ALL_TEST_TARGETS)), $(eval $t: jdk-image test-image))
+  $(foreach t, $(filter-out exploded-test-make%, $(ALL_EXPLODED_TEST_TARGETS)), $(eval $t: exploded-image test-image))
 
   create-buildjdk-copy: jdk.jlink-java java.base-gendata \
       $(addsuffix -java, $(INTERIM_IMAGE_MODULES))
@@ -890,16 +861,10 @@
 
   interim-image: $(INTERIM_JMOD_TARGETS)
 
-  test-make: clean-test-make
-
-  test-compile-commands: compile-commands
-
   build-test-lib: exploded-image-optimize
 
   build-test-failure-handler: interim-langtools
 
-  test-failure-handler: build-test-failure-handler
-
   test-image-failure-handler: build-test-failure-handler
 
   build-test-hotspot-jtreg-native: buildtools-jdk \
@@ -917,12 +882,6 @@
 
   test-image-hotspot-gtest: hotspot
 
-  test-hotspot-internal: exploded-image
-
-  test-hotspot-jtreg: jdk-image test-image
-
-  test-hotspot-gtest: exploded-image test-image-hotspot-gtest
-
   install: product-images
 
   product-bundles: product-images
@@ -1091,6 +1050,30 @@
 
 ALL_TARGETS += default jdk images docs bundles all
 
+# Aliases used for running tests.
+
+# Let "run-test" be an alias for "test"
+$(foreach t, $(ALL_NAMED_TESTS), $(eval run-test-$t: test-$t))
+$(foreach t, $(ALL_NAMED_TESTS), $(eval exploded-run-test-$t: exploded-test-$t))
+RUN_TEST_TARGETS := $(addprefix run-test-, $(ALL_NAMED_TESTS)) \
+    $(addprefix exploded-run-test-, $(ALL_NAMED_TESTS))
+
+run-test: test
+exploded-run-test: exploded-test
+
+# "make check" is a common idiom for running basic testing
+check: test-tier1
+
+# Keep some old names as aliases
+test-hotspot-jtreg: test-hotspot_all
+test-hotspot-jtreg-native: test-hotspot_native_sanity
+test-hotspot-gtest: exploded-test-gtest
+test-jdk-jtreg-native: test-jdk_native_sanity
+
+ALL_TARGETS += $(RUN_TEST_TARGETS) run-test exploded-run-test check \
+    test-hotspot-jtreg test-hotspot-jtreg-native test-hotspot-gtest \
+    test-jdk-jtreg-native
+
 ################################################################################
 ################################################################################
 #

--- a/make/MainSupport.gmk	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/MainSupport.gmk	Wed Oct 31 13:26:06 2018 -0700
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -30,17 +30,6 @@
 ifndef _MAINSUPPORT_GMK
 _MAINSUPPORT_GMK := 1
 
-# Run the tests specified by $1, with PRODUCT_HOME specified by $2
-# JT_JAVA is picked up by the jtreg launcher and used to run Jtreg itself.
-define RunTests
-	($(CD) $(TOPDIR)/test && $(MAKE) $(MAKE_ARGS) -j1 -k MAKEFLAGS= \
-	    JT_HOME=$(JT_HOME) PRODUCT_HOME=$(strip $2) \
-	    TEST_IMAGE_DIR=$(TEST_IMAGE_DIR) \
-	    ALT_OUTPUTDIR=$(OUTPUTDIR) TEST_JOBS=$(TEST_JOBS) \
-	    JT_JAVA=$(BOOT_JDK) JIB_JAR=$(JIB_JAR) \
-	    JOBS=$(JOBS) $1) || true
-endef
-
 define CleanDocs
 	@$(PRINTF) "Cleaning docs ..."
 	@$(PRINTF) "\n" $(LOG_DEBUG)

--- a/make/RunTests.gmk	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/RunTests.gmk	Wed Oct 31 13:26:06 2018 -0700
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -65,10 +65,14 @@
   ifndef _NT_SYMBOL_PATH
     # Can't use PathList here as it adds quotes around the value.
     _NT_SYMBOL_PATH := \
-        $(subst $(SPACE),;, $(foreach p, $(sort $(dir $(wildcard \
-        $(addprefix $(SYMBOLS_IMAGE_DIR)/bin/, *.pdb */*.pdb)))), $(call FixPath, $p)))
+        $(subst $(SPACE),;,$(strip \
+            $(foreach p, $(sort $(dir $(wildcard \
+                $(addprefix $(SYMBOLS_IMAGE_DIR)/bin/, *.pdb */*.pdb)))), \
+              $(call FixPath, $p) \
+            ) \
+        ))
     export _NT_SYMBOL_PATH
-    $(info _NT_SYMBOL_PATH $(_NT_SYMBOL_PATH))
+    $(info _NT_SYMBOL_PATH=$(_NT_SYMBOL_PATH))
   endif
 endif
 
@@ -296,16 +300,32 @@
 
 # Helper function to determine if a test specification is a special test
 #
-# It is a special test if it is "special:" followed by a test name.
+# It is a special test if it is "special:" followed by a test name,
+# if it is "make:" or "make-" followed by a make test, or any of the special test names
+# as a single word.
 define ParseSpecialTestSelection
   $(if $(filter special:%, $1), \
     $1 \
+  ) \
+  $(if $(filter make%, $1), \
+    $(if $(filter make:%, $1), \
+      special:$(strip $1) \
+    ) \
+    $(if $(filter make-%, $1), \
+      special:$(patsubst make-%,make:%, $1) \
+    ) \
+    $(if $(filter make, $1), \
+      special:make:all \
+    )
+  ) \
+  $(if $(filter hotspot-internal failure-handler, $1), \
+    special:$(strip $1) \
   )
 endef
 
 ifeq ($(TEST), )
   $(info No test selection given in TEST!)
-  $(info Please use e.g. 'run-test TEST=tier1' or 'run-test-tier1')
+  $(info Please use e.g. 'make test TEST=tier1' or 'make test-tier1')
   $(info See doc/testing.[md|html] for help)
   $(error Cannot continue)
 endif
@@ -659,9 +679,13 @@
         $$(JDK_IMAGE_DIR)/bin/java -XX:+ExecuteInternalVMTests \
         -XX:+ShowMessageBoxOnError -version
   else ifeq ($$($1_TEST_NAME), failure-handler)
-    $1_TEST_COMMAND_LINE := \
-        ($(CD) $(TOPDIR)/make/test && $(MAKE) $(MAKE_ARGS) -f \
-        BuildFailureHandler.gmk test)
+    ifeq ($(BUILD_FAILURE_HANDLER), true)
+      $1_TEST_COMMAND_LINE := \
+          ($(CD) $(TOPDIR)/make/test && $(MAKE) $(MAKE_ARGS) -f \
+          BuildFailureHandler.gmk test)
+    else
+      $$(error Cannot test failure handler if it is not built)
+    endif
   else ifeq ($$($1_TEST_NAME), make)
     $1_TEST_COMMAND_LINE := \
         ($(CD) $(TOPDIR)/test/make && $(MAKE) $(MAKE_ARGS) -f \

--- a/make/RunTestsPrebuiltSpec.gmk	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/RunTestsPrebuiltSpec.gmk	Wed Oct 31 13:26:06 2018 -0700
@@ -182,3 +182,7 @@
   SED := gsed
   TAR := gtar
 endif
+
+ifeq ($(OPENJDK_BUILD_OS), windows)
+  CYGPATH := cygpath
+endif

--- a/make/autoconf/flags-cflags.m4	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/autoconf/flags-cflags.m4	Wed Oct 31 13:26:06 2018 -0700
@@ -747,10 +747,6 @@
       # -Wno-psabi to get rid of annoying "note: the mangling of 'va_list' has changed in GCC 4.4"
       $1_CFLAGS_CPU="-fsigned-char -Wno-psabi $ARM_ARCH_TYPE_FLAGS $ARM_FLOAT_TYPE_FLAGS -DJDK_ARCH_ABI_PROP_NAME='\"\$(JDK_ARCH_ABI_PROP_NAME)\"'"
       $1_CFLAGS_CPU_JVM="-DARM"
-    elif test "x$FLAGS_CPU" = xaarch64; then
-      if test "x$HOTSPOT_TARGET_CPU_PORT" = xarm64; then
-        $1_CFLAGS_CPU_JVM="-fsigned-char -DARM"
-      fi
     elif test "x$FLAGS_CPU_ARCH" = xppc; then
       $1_CFLAGS_CPU_JVM="-minsert-sched-nops=regroup_exact -mno-multiple -mno-string"
       if test "x$FLAGS_CPU" = xppc64; then

--- a/make/autoconf/flags-ldflags.m4	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/autoconf/flags-ldflags.m4	Wed Oct 31 13:26:06 2018 -0700
@@ -173,10 +173,6 @@
     elif test "x$OPENJDK_$1_CPU" = xarm; then
       $1_CPU_LDFLAGS_JVM_ONLY="${$1_CPU_LDFLAGS_JVM_ONLY} -fsigned-char"
       $1_CPU_LDFLAGS="$ARM_ARCH_TYPE_FLAGS $ARM_FLOAT_TYPE_FLAGS"
-    elif test "x$FLAGS_CPU" = xaarch64; then
-      if test "x$HOTSPOT_TARGET_CPU_PORT" = xarm64; then
-        $1_CPU_LDFLAGS_JVM_ONLY="${$1_CPU_LDFLAGS_JVM_ONLY} -fsigned-char"
-      fi
     fi
 
   elif test "x$TOOLCHAIN_TYPE" = xsolstudio; then

--- a/make/autoconf/flags.m4	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/autoconf/flags.m4	Wed Oct 31 13:26:06 2018 -0700
@@ -34,7 +34,7 @@
 AC_DEFUN([FLAGS_SETUP_ABI_PROFILE],
 [
   AC_ARG_WITH(abi-profile, [AS_HELP_STRING([--with-abi-profile],
-      [specify ABI profile for ARM builds (arm-vfp-sflt,arm-vfp-hflt,arm-sflt, armv5-vfp-sflt,armv6-vfp-hflt,arm64,aarch64) @<:@toolchain dependent@:>@ ])])
+      [specify ABI profile for ARM builds (arm-vfp-sflt,arm-vfp-hflt,arm-sflt, armv5-vfp-sflt,armv6-vfp-hflt,aarch64) @<:@toolchain dependent@:>@ ])])
 
   if test "x$with_abi_profile" != x; then
     if test "x$OPENJDK_TARGET_CPU" != xarm && \
@@ -61,10 +61,6 @@
     elif test "x$OPENJDK_TARGET_ABI_PROFILE" = xarmv6-vfp-hflt; then
       ARM_FLOAT_TYPE=vfp-hflt
       ARM_ARCH_TYPE_FLAGS='-march=armv6 -marm'
-    elif test "x$OPENJDK_TARGET_ABI_PROFILE" = xarm64; then
-      # No special flags, just need to trigger setting JDK_ARCH_ABI_PROP_NAME
-      ARM_FLOAT_TYPE=
-      ARM_ARCH_TYPE_FLAGS=
     elif test "x$OPENJDK_TARGET_ABI_PROFILE" = xaarch64; then
       # No special flags, just need to trigger setting JDK_ARCH_ABI_PROP_NAME
       ARM_FLOAT_TYPE=

--- a/make/autoconf/hotspot.m4	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/autoconf/hotspot.m4	Wed Oct 31 13:26:06 2018 -0700
@@ -72,8 +72,6 @@
   AC_ARG_WITH([jvm-variants], [AS_HELP_STRING([--with-jvm-variants],
       [JVM variants (separated by commas) to build (server,client,minimal,core,zero,custom) @<:@server@:>@])])
 
-  SETUP_HOTSPOT_TARGET_CPU_PORT
-
   if test "x$with_jvm_variants" = x; then
     with_jvm_variants="server"
   fi
@@ -299,9 +297,6 @@
   if test "x$OPENJDK_TARGET_CPU" = xarm; then
     HOTSPOT_TARGET_CPU=arm_32
     HOTSPOT_TARGET_CPU_DEFINE="ARM32"
-  elif test "x$OPENJDK_TARGET_CPU" = xaarch64 && test "x$HOTSPOT_TARGET_CPU_PORT" = xarm64; then
-    HOTSPOT_TARGET_CPU=arm_64
-    HOTSPOT_TARGET_CPU_ARCH=arm
   fi
 
   # Verify that dependencies are met for explicitly set features.
@@ -542,6 +537,9 @@
 
   # Used for verification of Makefiles by check-jvm-feature
   AC_SUBST(VALID_JVM_FEATURES)
+
+  # --with-cpu-port is no longer supported
+  BASIC_DEPRECATED_ARG_WITH(with-cpu-port)
 ])
 
 ###############################################################################
@@ -579,31 +577,6 @@
 ])
 
 ################################################################################
-#
-# Specify which sources will be used to build the 64-bit ARM port
-#
-# --with-cpu-port=arm64   will use hotspot/src/cpu/arm
-# --with-cpu-port=aarch64 will use hotspot/src/cpu/aarch64
-#
-AC_DEFUN([SETUP_HOTSPOT_TARGET_CPU_PORT],
-[
-  AC_ARG_WITH(cpu-port, [AS_HELP_STRING([--with-cpu-port],
-      [specify sources to use for Hotspot 64-bit ARM port (arm64,aarch64) @<:@aarch64@:>@ ])])
-
-  if test "x$with_cpu_port" != x; then
-    if test "x$OPENJDK_TARGET_CPU" != xaarch64; then
-      AC_MSG_ERROR([--with-cpu-port only available on aarch64])
-    fi
-    if test "x$with_cpu_port" != xarm64 && \
-        test "x$with_cpu_port" != xaarch64; then
-      AC_MSG_ERROR([--with-cpu-port must specify arm64 or aarch64])
-    fi
-    HOTSPOT_TARGET_CPU_PORT="$with_cpu_port"
-  fi
-])
-
-
-################################################################################
 # Check if gtest should be built
 #
 AC_DEFUN_ONCE([HOTSPOT_ENABLE_DISABLE_GTEST],

--- a/make/common/FindTests.gmk	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/common/FindTests.gmk	Wed Oct 31 13:26:06 2018 -0700
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2017, 2018, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -72,6 +72,15 @@
 # Add Gtest
 ALL_NAMED_TESTS += gtest
 
+# Find make test targets
+MAKE_TEST_TARGETS := $(shell $(MAKE) -s --no-print-directory $(MAKE_ARGS) \
+    SPEC=$(SPEC) -f $(TOPDIR)/test/make/TestMake.gmk print-targets)
+
+ALL_NAMED_TESTS += $(addprefix make-, $(MAKE_TEST_TARGETS))
+
+# Add special tests
+ALL_NAMED_TESTS += hotspot-internal failure-handler make
+
 ################################################################################
 
 endif # _FIND_TESTS_GMK

--- a/make/conf/jib-profiles.js	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/conf/jib-profiles.js	Wed Oct 31 13:26:06 2018 -0700
@@ -233,8 +233,7 @@
     common.main_profile_names = [
         "linux-x64", "linux-x86", "macosx-x64", "solaris-x64",
         "solaris-sparcv9", "windows-x64", "windows-x86",
-        "linux-aarch64", "linux-arm32", "linux-arm64", "linux-arm-vfp-hflt",
-        "linux-arm-vfp-hflt-dyn"
+        "linux-aarch64", "linux-arm32"
     ];
 
     // These are the base setttings for all the main build profiles.
@@ -440,20 +439,7 @@
             dependencies: ["devkit", "build_devkit", "cups"],
             configure_args: [
                 "--openjdk-target=aarch64-linux-gnu", "--with-freetype=bundled",
-                "--disable-warnings-as-errors", "--with-cpu-port=aarch64",
-            ],
-        },
-
-        "linux-arm64": {
-            target_os: "linux",
-            target_cpu: "aarch64",
-            build_cpu: "x64",
-            dependencies: ["devkit", "build_devkit", "cups", "headless_stubs"],
-            configure_args: [
-                "--with-cpu-port=arm64",
-                "--with-jvm-variants=server",
-                "--openjdk-target=aarch64-linux-gnu",
-                "--enable-headless-only"
+                "--disable-warnings-as-errors"
             ],
         },
 
@@ -467,30 +453,7 @@
                 "--with-abi-profile=arm-vfp-hflt", "--disable-warnings-as-errors"
             ],
         },
-
-        "linux-arm-vfp-hflt": {
-            target_os: "linux",
-            target_cpu: "arm",
-            build_cpu: "x64",
-            dependencies: ["devkit", "build_devkit", "cups"],
-            configure_args: [
-                "--with-jvm-variants=minimal1,client",
-                "--with-x=" + input.get("devkit", "install_path") + "/arm-linux-gnueabihf/libc/usr/X11R6-PI",
-                "--with-fontconfig=" + input.get("devkit", "install_path") + "/arm-linux-gnueabihf/libc/usr/X11R6-PI",
-                "--openjdk-target=arm-linux-gnueabihf",
-                "--with-abi-profile=arm-vfp-hflt",
-                "--with-freetype=bundled"
-            ],
-        },
-
-        // Special version of the SE profile adjusted to be testable on arm64 hardware.
-        "linux-arm-vfp-hflt-dyn": {
-            configure_args: "--with-stdc++lib=dynamic"
-        }
     };
-    // Let linux-arm-vfp-hflt-dyn inherit everything from linux-arm-vfp-hflt
-    profiles["linux-arm-vfp-hflt-dyn"] = concatObjects(
-        profiles["linux-arm-vfp-hflt-dyn"], profiles["linux-arm-vfp-hflt"]);
 
     // Add the base settings to all the main profiles
     common.main_profile_names.forEach(function (name) {
@@ -617,15 +580,6 @@
         },
        "linux-arm32": {
             platform: "linux-arm32",
-        },
-       "linux-arm64": {
-            platform: "linux-arm64-vfp-hflt",
-        },
-        "linux-arm-vfp-hflt": {
-            platform: "linux-arm32-vfp-hflt",
-        },
-        "linux-arm-vfp-hflt-dyn": {
-            platform: "linux-arm32-vfp-hflt-dyn",
         }
     }
     // Generate common artifacts for all main profiles
@@ -759,7 +713,7 @@
                 testedProfile + ".test"
             ],
             src: "src.conf",
-            make_args: [ "run-test-prebuilt", "LOG_CMDLINES=true" ],
+            make_args: [ "run-test-prebuilt", "LOG_CMDLINES=true", "JTREG_VERBOSE=fail,error,time" ],
             environment: {
                 "BOOT_JDK": common.boot_jdk_home,
                 "JDK_IMAGE_DIR": input.get(testedProfile + ".jdk", "home_path"),
@@ -845,21 +799,13 @@
 var getJibProfilesDependencies = function (input, common) {
 
     var devkit_platform_revisions = {
-        linux_x64: "gcc7.3.0-OEL6.4+1.0",
+        linux_x64: "gcc7.3.0-OEL6.4+1.1",
         macosx_x64: "Xcode9.4-MacOSX10.13+1.0",
         solaris_x64: "SS12u4-Solaris11u1+1.0",
         solaris_sparcv9: "SS12u6-Solaris11u3+1.0",
         windows_x64: "VS2017-15.5.5+1.0",
-        linux_aarch64: (input.profile != null && input.profile.indexOf("arm64") >= 0
-                    ? "gcc-linaro-aarch64-linux-gnu-4.8-2013.11_linux+1.0"
-                    : "gcc7.3.0-Fedora27+1.0"),
-        linux_arm: (input.profile != null && input.profile.indexOf("hflt") >= 0
-                    ? "gcc-linaro-arm-linux-gnueabihf-raspbian-2012.09-20120921_linux+1.0"
-                    : (input.profile != null && input.profile.indexOf("arm32") >= 0
-                       ? "gcc7.3.0-Fedora27+1.0"
-                       : "arm-linaro-4.7+1.0"
-                       )
-                    )
+        linux_aarch64: "gcc7.3.0-Fedora27+1.0",
+        linux_arm: "gcc7.3.0-Fedora27+1.0"
     };
 
     var devkit_platform = (input.target_cpu == "x86"

--- a/make/devkit/Makefile	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/devkit/Makefile	Wed Oct 31 13:26:06 2018 -0700
@@ -36,7 +36,7 @@
 # By default this Makefile will build a native toolchain for the current
 # platform if called with something like this:
 #
-# make tars
+# make tars BASE_OS=OEL6
 #
 # To build the full set of crosstools for additional platforms, use a command
 # line looking like this:

--- a/make/devkit/Tools.gmk	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/devkit/Tools.gmk	Wed Oct 31 13:26:06 2018 -0700
@@ -110,6 +110,7 @@
     libXext libXext-devel \
     libXtst libXtst-devel \
     libXrender libXrender-devel \
+    libXrandr libXrandr-devel \
     freetype freetype-devel \
     libXt libXt-devel \
     libSM libSM-devel \

--- a/make/hotspot/lib/CompileJvm.gmk	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/hotspot/lib/CompileJvm.gmk	Wed Oct 31 13:26:06 2018 -0700
@@ -60,12 +60,6 @@
   OPENJDK_TARGET_CPU_VM_VERSION := amd64
 else ifeq ($(OPENJDK_TARGET_CPU), sparcv9)
   OPENJDK_TARGET_CPU_VM_VERSION := sparc
-else ifeq ($(HOTSPOT_TARGET_CPU_ARCH), arm)
-  ifeq ($(OPENJDK_TARGET_CPU), aarch64)
-    # This sets the Oracle Aarch64 port to use arm64
-    # while the original Aarch64 port uses aarch64
-    OPENJDK_TARGET_CPU_VM_VERSION := arm64
-  endif
 else
   OPENJDK_TARGET_CPU_VM_VERSION := $(OPENJDK_TARGET_CPU)
 endif

--- a/make/jdk/src/classes/build/tools/taglet/ExtLink.java	Wed Oct 31 11:45:04 2018 -0700
+++ b/make/jdk/src/classes/build/tools/taglet/ExtLink.java	Wed Oct 31 13:26:06 2018 -0700
@@ -48,7 +48,7 @@
  * will produce the following html
  * <p>
  * {@code
- * Please see <a href="https://www.oracle.com/pls/topic/lookup?ctx=javase10&id=Borealis">a spectacular</a> sight.
+ * Please see <a href="https://docs.oracle.com/pls/topic/lookup?ctx=javase10&id=Borealis">a spectacular</a> sight.
  * }
  */
 public class ExtLink implements Taglet {
@@ -63,7 +63,7 @@
 
     static final String TAG_NAME = "extLink";
 
-    static final String URL = "https://www.oracle.com/pls/topic/lookup?ctx=javase" +
+    static final String URL = "https://docs.oracle.com/pls/topic/lookup?ctx=javase" +
         SPEC_VERSION + "&amp;id=";
 
     static final Pattern TAG_PATTERN = Pattern.compile("(?s)(\\s*)(?<name>\\w+)(\\s+)(?<desc>.*)$");

--- a/src/hotspot/cpu/arm/abstractInterpreter_arm.cpp	Wed Oct 31 11:45:04 2018 -0700
+++ b/src/hotspot/cpu/arm/abstractInterpreter_arm.cpp	Wed Oct 31 13:26:06 2018 -0700
@@ -38,19 +38,6 @@
 int AbstractInterpreter::BasicType_as_index(BasicType type) {
   int i = 0;
   switch (type) {
-#ifdef AARCH64
-    case T_BOOLEAN: i = 0; break;
-    case T_CHAR   : i = 1; break;
-    case T_BYTE   : i = 2; break;
-    case T_SHORT  : i = 3; break;
-    case T_INT    : // fall through
-    case T_LONG   : // fall through
-    case T_VOID   : // fall through
-    case T_FLOAT  : // fall through
-    case T_DOUBLE : i = 4; break;
-    case T_OBJECT : // fall through
-    case T_ARRAY  : i = 5; break;
-#else
     case T_VOID   : i = 0; break;
     case T_BOOLEAN: i = 1; break;
     case T_CHAR   : i = 2; break;
@@ -62,7 +49,6 @@
     case T_LONG   : i = 7; break;
     case T_FLOAT  : i = 8; break;
     case T_DOUBLE : i = 9; break;
-#endif // AARCH64
     default       : ShouldNotReachHere();
   }
   assert(0 <= i && i < AbstractInterpreter::number_of_result_handlers, "index out of bounds");
@@ -71,7 +57,7 @@
 
 // How much stack a method activation needs in words.
 int AbstractInterpreter::size_top_interpreter_activation(Method* method) {
-  const int stub_code = AARCH64_ONLY(24) NOT_AARCH64(12);  // see generate_call_stub
+  const int stub_code = 12;  // see generate_call_stub
   // Save space for one monitor to get into the interpreted method in case
   // the method is synchronized
   int monitor_size    = method->is_synchronized() ?
@@ -108,9 +94,6 @@
          (moncount*frame::interpreter_frame_monitor_size()) +
          tempcount*Interpreter::stackElementWords + extra_args;
 
-#ifdef AARCH64
-  size = align_up(size, StackAlignmentInBytes/BytesPerWord);
-#endif // AARCH64
 
   return size;
 }
@@ -146,65 +129,7 @@
   // interpreter_frame_sender_sp is the original sp of the caller (the unextended_sp)
   // and sender_sp is (fp + sender_sp_offset*wordSize)
 
-#ifdef AARCH64
-  intptr_t* locals;
-  if (caller->is_interpreted_frame()) {
-    // attach locals to the expression stack of caller interpreter frame
-    locals = caller->interpreter_frame_tos_address() + caller_actual_parameters*Interpreter::stackElementWords - 1;
-  } else {
-    assert (is_bottom_frame, "should be");
-    locals = interpreter_frame->fp() + frame::sender_sp_offset + method->max_locals() - 1;
-  }
-
-  if (TraceDeoptimization) {
-    tty->print_cr("layout_activation:");
-
-    if (caller->is_entry_frame()) {
-      tty->print("entry ");
-    }
-    if (caller->is_compiled_frame()) {
-      tty->print("compiled ");
-    }
-    if (caller->is_interpreted_frame()) {
-      tty->print("interpreted ");
-    }
-    tty->print_cr("caller: sp=%p, unextended_sp=%p, fp=%p, pc=%p", caller->sp(), caller->unextended_sp(), caller->fp(), caller->pc());
-    tty->print_cr("interpreter_frame: sp=%p, unextended_sp=%p, fp=%p, pc=%p", interpreter_frame->sp(), interpreter_frame->unextended_sp(), interpreter_frame->fp(), interpreter_frame->pc());
-    tty->print_cr("method: max_locals = %d, size_of_parameters = %d", method->max_locals(), method->size_of_parameters());
-    tty->print_cr("caller_actual_parameters = %d", caller_actual_parameters);
-    tty->print_cr("locals = %p", locals);
-  }
-
-#ifdef ASSERT
-  if (caller_actual_parameters != method->size_of_parameters()) {
-    assert(caller->is_interpreted_frame(), "adjusted caller_actual_parameters, but caller is not interpreter frame");
-    Bytecode_invoke inv(caller->interpreter_frame_method(), caller->interpreter_frame_bci());
-
-    if (is_bottom_frame) {
-      assert(caller_actual_parameters == 0, "invalid adjusted caller_actual_parameters value for bottom frame");
-      assert(inv.is_invokedynamic() || inv.is_invokehandle(), "adjusted caller_actual_parameters for bottom frame, but not invokedynamic/invokehandle");
-    } else {
-      assert(caller_actual_parameters == method->size_of_parameters()+1, "invalid adjusted caller_actual_parameters value");
-      assert(!inv.is_invokedynamic() && MethodHandles::has_member_arg(inv.klass(), inv.name()), "adjusted caller_actual_parameters, but no member arg");
-    }
-  }
-  if (caller->is_interpreted_frame()) {
-    intptr_t* locals_base = (locals - method->max_locals()*Interpreter::stackElementWords + 1);
-    locals_base = align_down(locals_base, StackAlignmentInBytes);
-    assert(interpreter_frame->sender_sp() <= locals_base, "interpreter-to-interpreter frame chaining");
-
-  } else if (caller->is_compiled_frame()) {
-    assert(locals + 1 <= caller->unextended_sp(), "compiled-to-interpreter frame chaining");
-
-  } else {
-    assert(caller->is_entry_frame(), "should be");
-    assert(locals + 1 <= caller->fp(), "entry-to-interpreter frame chaining");
-  }
-#endif // ASSERT
-
-#else
   intptr_t* locals = interpreter_frame->sender_sp() + max_locals - 1;
-#endif // AARCH64
 
   interpreter_frame->interpreter_frame_set_locals(locals);
   BasicObjectLock* montop = interpreter_frame->interpreter_frame_monitor_begin();
@@ -215,44 +140,16 @@
   intptr_t* stack_top = (intptr_t*) monbot  -
     tempcount*Interpreter::stackElementWords -
     popframe_extra_args;
-#ifdef AARCH64
-  interpreter_frame->interpreter_frame_set_stack_top(stack_top);
-
-  // We have to add extra reserved slots to max_stack. There are 3 users of the extra slots,
-  // none of which are at the same time, so we just need to make sure there is enough room
-  // for the biggest user:
-  //   -reserved slot for exception handler
-  //   -reserved slots for JSR292. Method::extra_stack_entries() is the size.
-  //   -3 reserved slots so get_method_counters() can save some registers before call_VM().
-  int max_stack = method->constMethod()->max_stack() + MAX2(3, Method::extra_stack_entries());
-  intptr_t* extended_sp = (intptr_t*) monbot  -
-    (max_stack * Interpreter::stackElementWords) -
-    popframe_extra_args;
-  extended_sp = align_down(extended_sp, StackAlignmentInBytes);
-  interpreter_frame->interpreter_frame_set_extended_sp(extended_sp);
-#else
   interpreter_frame->interpreter_frame_set_last_sp(stack_top);
-#endif // AARCH64
 
   // All frames but the initial (oldest) interpreter frame we fill in have a
   // value for sender_sp that allows walking the stack but isn't
   // truly correct. Correct the value here.
 
-#ifdef AARCH64
-  if (caller->is_interpreted_frame()) {
-    intptr_t* sender_sp = align_down(caller->interpreter_frame_tos_address(), StackAlignmentInBytes);
-    interpreter_frame->set_interpreter_frame_sender_sp(sender_sp);
-
-  } else {
-    // in case of non-interpreter caller sender_sp of the oldest frame is already
-    // set to valid value
-  }
-#else
   if (extra_locals != 0 &&
       interpreter_frame->sender_sp() == interpreter_frame->interpreter_frame_sender_sp() ) {
     interpreter_frame->set_interpreter_frame_sender_sp(caller->sp() + extra_locals);
   }
-#endif // AARCH64
 
   *interpreter_frame->interpreter_frame_cache_addr() =
     method->constants()->cache();

--- a/src/hotspot/cpu/arm/arm.ad	Wed Oct 31 11:45:04 2018 -0700
+++ b/src/hotspot/cpu/arm/arm.ad	Wed Oct 31 13:26:06 2018 -0700
@@ -67,15 +67,10 @@
   return MacroAssembler::_cache_fully_reachable();
 }
 
-#ifdef AARCH64
-#define ldr_32 ldr_w
-#define str_32 str_w
-#else
 #define ldr_32 ldr
 #define str_32 str
 #define tst_32 tst
 #define teq_32 teq
-#endif
 #if 1
 extern bool PrintOptoAssembly;
 #endif
@@ -111,12 +106,7 @@
   static int emit_deopt_handler(CodeBuffer& cbuf);
 
   static uint size_exception_handler() {
-#ifdef AARCH64
-    // ldr_literal; br; (pad); <literal>
-    return 3 * Assembler::InstructionSize + wordSize;
-#else
     return ( 3 * 4 );
-#endif
   }
 
 
@@ -205,9 +195,6 @@
 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
 
 int Compile::ConstantTable::calculate_table_base_offset() const {
-#ifdef AARCH64
-  return 0;
-#else
   int offset = -(size() / 2);
   // flds, fldd: 8-bit  offset multiplied by 4: +/- 1024
   // ldr, ldrb : 12-bit offset:                 +/- 4096
@@ -215,7 +202,6 @@
     offset = Assembler::min_simm10();
   }
   return offset;
-#endif
 }
 
 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
@@ -240,11 +226,7 @@
 }
 
 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
-#ifdef AARCH64
-  return 5 * Assembler::InstructionSize;
-#else
   return 8;
-#endif
 }
 
 #ifndef PRODUCT
@@ -262,12 +244,6 @@
   for (int i = 0; i < OptoPrologueNops; i++) {
     st->print_cr("NOP"); st->print("\t");
   }
-#ifdef AARCH64
-  if (OptoPrologueNops <= 0) {
-    st->print_cr("NOP\t! required for safe patching");
-    st->print("\t");
-  }
-#endif
 
   size_t framesize = C->frame_size_in_bytes();
   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
@@ -298,11 +274,6 @@
   for (int i = 0; i < OptoPrologueNops; i++) {
     __ nop();
   }
-#ifdef AARCH64
-  if (OptoPrologueNops <= 0) {
-    __ nop(); // required for safe patching by patch_verified_entry()
-  }
-#endif
 
   size_t framesize = C->frame_size_in_bytes();
   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
@@ -361,18 +332,8 @@
 
   if (do_polling() && ra_->C->is_method_compilation()) {
     st->print("\n\t");
-#ifdef AARCH64
-    if (MacroAssembler::page_reachable_from_cache(os::get_polling_page())) {
-      st->print("ADRP     Rtemp, #PollAddr\t! Load Polling address\n\t");
-      st->print("LDR      ZR,[Rtemp + #PollAddr & 0xfff]\t!Poll for Safepointing");
-    } else {
-      st->print("mov_slow Rtemp, #PollAddr\t! Load Polling address\n\t");
-      st->print("LDR      ZR,[Rtemp]\t!Poll for Safepointing");
-    }
-#else
     st->print("MOV    Rtemp, #PollAddr\t! Load Polling address\n\t");
     st->print("LDR    Rtemp,[Rtemp]\t!Poll for Safepointing");
-#endif
   }
 }
 #endif
@@ -390,36 +351,15 @@
 
   // If this does safepoint polling, then do it here
   if (do_polling() && ra_->C->is_method_compilation()) {
-#ifdef AARCH64
-    if (false && MacroAssembler::page_reachable_from_cache(os::get_polling_page())) {
-/* FIXME: TODO
-      __ relocate(relocInfo::xxx);
-      __ adrp(Rtemp, (intptr_t)os::get_polling_page());
-      __ relocate(relocInfo::poll_return_type);
-      int offset = os::get_polling_page() & 0xfff;
-      __ ldr(ZR, Address(Rtemp + offset));
-*/
-    } else {
-      __ mov_address(Rtemp, (address)os::get_polling_page(), symbolic_Relocation::polling_page_reference);
-      __ relocate(relocInfo::poll_return_type);
-      __ ldr(ZR, Address(Rtemp));
-    }
-#else
     // mov_slow here is usually one or two instruction
     __ mov_address(Rtemp, (address)os::get_polling_page(), symbolic_Relocation::polling_page_reference);
     __ relocate(relocInfo::poll_return_type);
     __ ldr(Rtemp, Address(Rtemp));
-#endif
   }
 }
 
 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
-#ifdef AARCH64
-  // allow for added alignment nop from mov_address bind_literal
-  return MachNode::size(ra_) + 1 * Assembler::InstructionSize;
-#else
   return MachNode::size(ra_);
-#endif
 }
 
 int MachEpilogNode::reloc() const {
@@ -451,16 +391,12 @@
 }
 
 static inline bool is_iRegLd_memhd(OptoReg::Name src_first, OptoReg::Name src_second, int offset) {
-#ifdef AARCH64
-  return is_memoryHD(offset);
-#else
   int rlo = Matcher::_regEncode[src_first];
   int rhi = Matcher::_regEncode[src_second];
   if (!((rlo&1)==0 && (rlo+1 == rhi))) {
     tty->print_cr("CAUGHT BAD LDRD/STRD");
   }
   return (rlo&1)==0 && (rlo+1 == rhi) && is_memoryHD(offset);
-#endif
 }
 
 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
@@ -549,11 +485,6 @@
                 Matcher::regName[src_first]);
 #endif
     }
-#ifdef AARCH64
-    if (src_first+1 == src_second && dst_first+1 == dst_second) {
-      return size + 4;
-    }
-#endif
     size += 4;
   }
 
@@ -722,20 +653,12 @@
       assert((src_first&1)==0 && src_first+1 == src_second, "pairs of registers must be aligned/contiguous");
       assert(src_second_rc == rc_int && dst_second_rc == rc_float, "unsupported");
       if (cbuf) {
-#ifdef AARCH64
-        __ fmov_dx(reg_to_FloatRegister_object(Matcher::_regEncode[dst_first]), reg_to_register_object(Matcher::_regEncode[src_first]));
-#else
         __ fmdrr(reg_to_FloatRegister_object(Matcher::_regEncode[dst_first]), reg_to_register_object(Matcher::_regEncode[src_first]), reg_to_register_object(Matcher::_regEncode[src_second]));
-#endif
 #ifndef PRODUCT
       } else if (!do_size) {
         if (size != 0) st->print("\n\t");
-#ifdef AARCH64
-        st->print("FMOV_DX   R_%s, R_%s\t! spill",OptoReg::regname(dst_first), OptoReg::regname(src_first));
-#else
         st->print("FMDRR   R_%s, R_%s, R_%s\t! spill",OptoReg::regname(dst_first), OptoReg::regname(src_first), OptoReg::regname(src_second));
 #endif
-#endif
       }
       return size + 4;
     } else {
@@ -759,20 +682,12 @@
       assert((dst_first&1)==0 && dst_first+1 == dst_second, "pairs of registers must be aligned/contiguous");
       assert(src_second_rc == rc_float && dst_second_rc == rc_int, "unsupported");
       if (cbuf) {
-#ifdef AARCH64
-        __ fmov_xd(reg_to_register_object(Matcher::_regEncode[dst_first]), reg_to_FloatRegister_object(Matcher::_regEncode[src_first]));
-#else
         __ fmrrd(reg_to_register_object(Matcher::_regEncode[dst_first]), reg_to_register_object(Matcher::_regEncode[dst_second]), reg_to_FloatRegister_object(Matcher::_regEncode[src_first]));
-#endif
 #ifndef PRODUCT
       } else if (!do_size) {
         if (size != 0) st->print("\n\t");
-#ifdef AARCH64
-        st->print("FMOV_XD R_%s, R_%s\t! spill",OptoReg::regname(dst_first), OptoReg::regname(src_first));
-#else
         st->print("FMRRD   R_%s, R_%s, R_%s\t! spill",OptoReg::regname(dst_first), OptoReg::regname(dst_second), OptoReg::regname(src_first));
 #endif
-#endif
       }
       return size + 4;
     } else {
@@ -795,7 +710,6 @@
     return size;               // Self copy; no move
   assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
 
-#ifndef AARCH64
   // Check for integer reg-reg copy.  Hi bits are stuck up in the top
   // 32-bits of a 64-bit register, but are needed in low bits of another
   // register (else it's a hi-bits-to-hi-bits copy which should have
@@ -852,7 +766,6 @@
     }
     return size + 4;
   }
-#endif
 
   Unimplemented();
   return 0; // Mute compiler
@@ -910,11 +823,7 @@
     __ add(dst, SP, offset);
   } else {
     __ mov_slow(dst, offset);
-#ifdef AARCH64
-    __ add(dst, SP, dst, ex_lsl);
-#else
     __ add(dst, SP, dst);
-#endif
   }
 }
 
@@ -926,11 +835,7 @@
 
 //=============================================================================
 #ifndef PRODUCT
-#ifdef AARCH64
-#define R_RTEMP "R_R16"
-#else
 #define R_RTEMP "R_R12"
-#endif
 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
   st->print_cr("\nUEP:");
   if (UseCompressedClassPointers) {
@@ -952,14 +857,7 @@
 
   __ load_klass(Rtemp, receiver);
   __ cmp(Rtemp, iCache);
-#ifdef AARCH64
-  Label match;
-  __ b(match, eq);
-  __ jump(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type, Rtemp);
-  __ bind(match);
-#else
   __ jump(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type, noreg, ne);
-#endif
 }
 
 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
@@ -1005,24 +903,12 @@
   int offset = __ offset();
   address deopt_pc = __ pc();
 
-#ifdef AARCH64
-  // See LR saved by caller in sharedRuntime_arm.cpp
-  // see also hse1 ws
-  // see also LIR_Assembler::emit_deopt_handler
-
-  __ raw_push(LR, LR); // preserve LR in both slots
-  __ mov_relative_address(LR, deopt_pc);
-  __ str(LR, Address(SP, 1 * wordSize)); // save deopt PC
-  // OK to kill LR, because deopt blob will restore it from SP[0]
-  __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, LR_tmp);
-#else
   __ sub(SP, SP, wordSize); // make room for saved PC
   __ push(LR); // save LR that may be live when we get here
   __ mov_relative_address(LR, deopt_pc);
   __ str(LR, Address(SP, wordSize)); // save deopt PC
   __ pop(LR); // restore LR
   __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, noreg);
-#endif
 
   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
 
@@ -1073,21 +959,13 @@
   case Op_AddVF:
   case Op_SubVF:
   case Op_MulVF:
-#ifdef AARCH64
-    return VM_Version::has_simd();
-#else
     return VM_Version::has_vfp() || VM_Version::has_simd();
-#endif
   case Op_AddVD:
   case Op_SubVD:
   case Op_MulVD:
   case Op_DivVF:
   case Op_DivVD:
-#ifdef AARCH64
-    return VM_Version::has_simd();
-#else
     return VM_Version::has_vfp();
-#endif
   }
 
   return true;  // Per default match rules are supported.
@@ -1158,11 +1036,7 @@
 }
 
 const bool Matcher::convL2FSupported(void) {
-#ifdef AARCH64
-  return true;
-#else
   return false;
-#endif
 }
 
 // Is this branch offset short enough that a short branch can be used?
@@ -1181,29 +1055,17 @@
 
 const bool Matcher::isSimpleConstant64(jlong value) {
   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
-#ifdef AARCH64
-  return (value == 0);
-#else
   return false;
-#endif
 }
 
 // No scaling for the parameter the ClearArray node.
 const bool Matcher::init_array_count_is_in_bytes = true;
 
-#ifdef AARCH64
-const int Matcher::long_cmove_cost() { return 1; }
-#else
 // Needs 2 CMOV's for longs.
 const int Matcher::long_cmove_cost() { return 2; }
-#endif
-
-#ifdef AARCH64
-const int Matcher::float_cmove_cost() { return 1; }
-#else
+
 // CMOVF/CMOVD are expensive on ARM.
 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
-#endif
 
 // Does the CPU require late expand (see block.cpp for description of late expand)?
 const bool Matcher::require_postalloc_expand = false;
@@ -1211,11 +1073,7 @@
 // Do we need to mask the count passed to shift instructions or does
 // the cpu only look at the lower 5/6 bits anyway?
 // FIXME: does this handle vector shifts as well?
-#ifdef AARCH64
-const bool Matcher::need_masked_shift_count = false;
-#else
 const bool Matcher::need_masked_shift_count = true;
-#endif
 
 const bool Matcher::convi2l_type_required = true;
 
@@ -1261,14 +1119,7 @@
 // needed.  Else we split the double into 2 integer pieces and move it
 // piece-by-piece.  Only happens when passing doubles into C code as the
 // Java calling convention forces doubles to be aligned.
-#ifdef AARCH64
-// On stack replacement support:
-// We don't need Load[DL]_unaligned support, because interpreter stack
-// has correct alignment
-const bool Matcher::misaligned_doubles_ok = true;
-#else
 const bool Matcher::misaligned_doubles_ok = false;
-#endif
 
 // No-op on ARM.
 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
@@ -1300,10 +1151,6 @@
 // Registers not mentioned will be killed by the VM call in the trampoline, and
 // arguments in those registers not be available to the callee.
 bool Matcher::can_be_java_arg( int reg ) {
-#ifdef AARCH64
-  if (reg >= R_R0_num && reg < R_R8_num) return true;
-  if (reg >= R_V0_num && reg <= R_V7b_num && ((reg & 3) < 2)) return true;
-#else
   if (reg == R_R0_num ||
       reg == R_R1_num ||
       reg == R_R2_num ||
@@ -1311,7 +1158,6 @@
 
   if (reg >= R_S0_num &&
       reg <= R_S13_num) return true;
-#endif
   return false;
 }
 
@@ -1454,44 +1300,14 @@
     Register R8_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
     assert(R8_ic_reg == Ricklass, "should be");
     __ set_inst_mark();
-#ifdef AARCH64
-// TODO: see C1 LIR_Assembler::ic_call()
-    InlinedAddress oop_literal((address)Universe::non_oop_word());
-    int offset = __ offset();
-    int fixed_size = mov_oop_size * 4;
-    if (VM_Version::prefer_moves_over_load_literal()) {
-      uintptr_t val = (uintptr_t)Universe::non_oop_word();
-      __ movz(R8_ic_reg, (val >>  0) & 0xffff,  0);
-      __ movk(R8_ic_reg, (val >> 16) & 0xffff, 16);
-      __ movk(R8_ic_reg, (val >> 32) & 0xffff, 32);
-      __ movk(R8_ic_reg, (val >> 48) & 0xffff, 48);
-    } else {
-      __ ldr_literal(R8_ic_reg, oop_literal);
-    }
-    assert(__ offset() - offset == fixed_size, "bad mov_oop size");
-#else
     __ movw(R8_ic_reg, ((unsigned int)Universe::non_oop_word()) & 0xffff);
     __ movt(R8_ic_reg, ((unsigned int)Universe::non_oop_word()) >> 16);
-#endif
     address  virtual_call_oop_addr = __ inst_mark();
     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
     // who we intended to call.
     int method_index = resolved_method_index(cbuf);
     __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
     emit_call_reloc(cbuf, as_MachCall(), $meth, RelocationHolder::none);
-#ifdef AARCH64
-    if (!VM_Version::prefer_moves_over_load_literal()) {
-      Label skip_literal;
-      __ b(skip_literal);
-      int off2 = __ offset();
-      __ bind_literal(oop_literal);
-      if (__ offset() - off2 == wordSize) {
-        // no padding, so insert nop for worst-case sizing
-        __ nop();
-      }
-      __ bind(skip_literal);
-    }
-#endif
   %}
 
   enc_class LdReplImmI(immI src, regD dst, iRegI tmp, int cnt, int wth) %{
@@ -1558,16 +1374,8 @@
     // See if the lengths are different, and calculate min in str1_reg.
     // Stash diff in tmp2 in case we need it for a tie-breaker.
     __ subs_32(tmp2_reg, cnt1_reg, cnt2_reg);
-#ifdef AARCH64
-    Label Lskip;
-    __ _lsl_w(cnt1_reg, cnt1_reg, exact_log2(sizeof(jchar))); // scale the limit
-    __ b(Lskip, mi);
-    __ _lsl_w(cnt1_reg, cnt2_reg, exact_log2(sizeof(jchar))); // scale the limit
-    __ bind(Lskip);
-#else
     __ mov(cnt1_reg, AsmOperand(cnt1_reg, lsl, exact_log2(sizeof(jchar)))); // scale the limit
     __ mov(cnt1_reg, AsmOperand(cnt2_reg, lsl, exact_log2(sizeof(jchar))), pl); // scale the limit
-#endif
 
     // reallocate cnt1_reg, cnt2_reg, result_reg
     // Note:  limit_reg holds the string length pre-scaled by 2
@@ -1717,16 +1525,6 @@
     int base_offset    = arrayOopDesc::base_offset_in_bytes(T_CHAR);
 
     // return true if the same array
-#ifdef AARCH64
-    __ cmp(ary1_reg, ary2_reg);
-    __ b(Lequal, eq);
-
-    __ mov(result_reg, 0);
-
-    __ cbz(ary1_reg, Ldone); // not equal
-
-    __ cbz(ary2_reg, Ldone); // not equal
-#else
     __ teq(ary1_reg, ary2_reg);
     __ mov(result_reg, 1, eq);
     __ b(Ldone, eq); // equal
@@ -1738,19 +1536,12 @@
     __ tst(ary2_reg, ary2_reg);
     __ mov(result_reg, 0, eq);
     __ b(Ldone, eq);    // not equal
-#endif
 
     //load the lengths of arrays
     __ ldr_s32(tmp1_reg, Address(ary1_reg, length_offset)); // int
     __ ldr_s32(tmp2_reg, Address(ary2_reg, length_offset)); // int
 
     // return false if the two arrays are not equal length
-#ifdef AARCH64
-    __ cmp_w(tmp1_reg, tmp2_reg);
-    __ b(Ldone, ne);    // not equal
-
-    __ cbz_w(tmp1_reg, Lequal); // zero-length arrays are equal
-#else
     __ teq_32(tmp1_reg, tmp2_reg);
     __ mov(result_reg, 0, ne);
     __ b(Ldone, ne);    // not equal
@@ -1758,7 +1549,6 @@
     __ tst(tmp1_reg, tmp1_reg);
     __ mov(result_reg, 1, eq);
     __ b(Ldone, eq);    // zero-length arrays are equal
-#endif
 
     // load array addresses
     __ add(ary1_reg, ary1_reg, base_offset);
@@ -1852,11 +1642,7 @@
   sync_stack_slots(1 * VMRegImpl::slots_per_word);
 
   // Compiled code's Frame Pointer
-#ifdef AARCH64
-  frame_pointer(R_SP);
-#else
   frame_pointer(R_R13);
-#endif
 
   // Stack alignment requirement
   stack_alignment(StackAlignmentInBytes);
@@ -1953,7 +1739,6 @@
   interface(CONST_INTER);
 %}
 
-#ifndef AARCH64
 // Integer Immediate: offset for half and double word loads and stores
 operand immIHD() %{
   predicate(is_memoryHD(n->get_int()));
@@ -1972,7 +1757,6 @@
   format %{ %}
   interface(CONST_INTER);
 %}
-#endif
 
 // Valid scale values for addressing modes and shifts
 operand immU5() %{
@@ -2183,45 +1967,6 @@
   interface(CONST_INTER);
 %}
 
-#ifdef AARCH64
-// Long Immediate: for logical instruction
-operand limmL() %{
-  predicate(is_limmL(n->get_long()));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand limmLn() %{
-  predicate(is_limmL(~n->get_long()));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Long Immediate: for arithmetic instruction
-operand aimmL() %{
-  predicate(is_aimm(n->get_long()));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand aimmLneg() %{
-  predicate(is_aimm(-n->get_long()));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-#endif // AARCH64
 
 // Long Immediate: the value FF
 operand immL_FF() %{
@@ -2404,11 +2149,7 @@
   match(R1RegI);
   match(R2RegI);
   match(R3RegI);
-#ifdef AARCH64
-  match(ZRRegI);
-#else
   match(R12RegI);
-#endif
 
   format %{ %}
   interface(REG_INTER);
@@ -2446,49 +2187,6 @@
   interface(REG_INTER);
 %}
 
-#ifdef AARCH64
-// Like sp_ptr_reg, but exclude regs (Aarch64 SP) that can't be
-// stored directly.  Includes ZR, so can't be used as a destination.
-operand store_ptr_RegP() %{
-  constraint(ALLOC_IN_RC(store_ptr_reg));
-  match(RegP);
-  match(iRegP);
-  match(ZRRegP);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand store_RegI() %{
-  constraint(ALLOC_IN_RC(store_reg));
-  match(RegI);
-  match(iRegI);
-  match(ZRRegI);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand store_RegL() %{
-  constraint(ALLOC_IN_RC(store_ptr_reg));
-  match(RegL);
-  match(iRegL);
-  match(ZRRegL);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand store_RegN() %{
-  constraint(ALLOC_IN_RC(store_reg));
-  match(RegN);
-  match(iRegN);
-  match(ZRRegN);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-#endif
 
 operand R0RegP() %{
   constraint(ALLOC_IN_RC(R0_regP));
@@ -2578,7 +2276,6 @@
   interface(REG_INTER);
 %}
 
-#ifndef AARCH64
 operand R12RegI() %{
   constraint(ALLOC_IN_RC(R12_regI));
   match(iRegI);
@@ -2586,18 +2283,13 @@
   format %{ %}
   interface(REG_INTER);
 %}
-#endif
 
 // Long Register
 operand iRegL() %{
   constraint(ALLOC_IN_RC(long_reg));
   match(RegL);
-#ifdef AARCH64
-  match(iRegLd);
-#else
   match(R0R1RegL);
   match(R2R3RegL);
-#endif
 //match(iRegLex);
 
   format %{ %}
@@ -2612,7 +2304,6 @@
   interface(REG_INTER);
 %}
 
-#ifndef AARCH64
 // first long arg, or return value
 operand R0R1RegL() %{
   constraint(ALLOC_IN_RC(R0R1_regL));
@@ -2629,7 +2320,6 @@
   format %{ %}
   interface(REG_INTER);
 %}
-#endif
 
 // Condition Code Flag Register
 operand flagsReg() %{
@@ -2671,7 +2361,6 @@
 %}
 
 // Condition Code Register, long comparisons.
-#ifndef AARCH64
 operand flagsRegL_LTGE() %{
   constraint(ALLOC_IN_RC(int_flags));
   match(RegFlags);
@@ -2719,7 +2408,6 @@
   format %{ "apsr_UL_LEGT" %}
   interface(REG_INTER);
 %}
-#endif
 
 // Condition Code Register, floating comparisons, unordered same as "less".
 operand flagsRegF() %{
@@ -2800,19 +2488,15 @@
   format %{ "[$reg]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp(0x0);
   %}
 %}
 
-#ifdef AARCH64
-// Indirect with scaled*1 uimm12 offset
-operand indOffsetU12ScaleB(sp_ptr_RegP reg, immUL12 offset) %{
+
+// Indirect with Offset in ]-4096, 4096[
+operand indOffset12(sp_ptr_RegP reg, immI12 offset) %{
   constraint(ALLOC_IN_RC(sp_ptr_reg));
   match(AddP reg offset);
 
@@ -2820,18 +2504,14 @@
   format %{ "[$reg + $offset]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp($offset);
   %}
 %}
 
-// Indirect with scaled*2 uimm12 offset
-operand indOffsetU12ScaleS(sp_ptr_RegP reg, immUL12x2 offset) %{
+// Indirect with offset for float load/store
+operand indOffsetFP(sp_ptr_RegP reg, immIFP offset) %{
   constraint(ALLOC_IN_RC(sp_ptr_reg));
   match(AddP reg offset);
 
@@ -2839,18 +2519,14 @@
   format %{ "[$reg + $offset]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp($offset);
   %}
 %}
 
-// Indirect with scaled*4 uimm12 offset
-operand indOffsetU12ScaleI(sp_ptr_RegP reg, immUL12x4 offset) %{
+// Indirect with Offset for half and double words
+operand indOffsetHD(sp_ptr_RegP reg, immIHD offset) %{
   constraint(ALLOC_IN_RC(sp_ptr_reg));
   match(AddP reg offset);
 
@@ -2858,18 +2534,14 @@
   format %{ "[$reg + $offset]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp($offset);
   %}
 %}
 
-// Indirect with scaled*8 uimm12 offset
-operand indOffsetU12ScaleL(sp_ptr_RegP reg, immUL12x8 offset) %{
+// Indirect with Offset and Offset+4 in ]-1024, 1024[
+operand indOffsetFPx2(sp_ptr_RegP reg, immX10x2 offset) %{
   constraint(ALLOC_IN_RC(sp_ptr_reg));
   match(AddP reg offset);
 
@@ -2877,18 +2549,14 @@
   format %{ "[$reg + $offset]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp($offset);
   %}
 %}
 
-// Indirect with scaled*16 uimm12 offset
-operand indOffsetU12ScaleQ(sp_ptr_RegP reg, immUL12x16 offset) %{
+// Indirect with Offset and Offset+4 in ]-4096, 4096[
+operand indOffset12x2(sp_ptr_RegP reg, immI12x2 offset) %{
   constraint(ALLOC_IN_RC(sp_ptr_reg));
   match(AddP reg offset);
 
@@ -2896,114 +2564,12 @@
   format %{ "[$reg + $offset]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp($offset);
   %}
 %}
 
-#else // ! AARCH64
-
-// Indirect with Offset in ]-4096, 4096[
-operand indOffset12(sp_ptr_RegP reg, immI12 offset) %{
-  constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(AddP reg offset);
-
-  op_cost(100);
-  format %{ "[$reg + $offset]" %}
-  interface(MEMORY_INTER) %{
-    base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
-    index(0xf); // PC => no index
-#endif
-    scale(0x0);
-    disp($offset);
-  %}
-%}
-
-// Indirect with offset for float load/store
-operand indOffsetFP(sp_ptr_RegP reg, immIFP offset) %{
-  constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(AddP reg offset);
-
-  op_cost(100);
-  format %{ "[$reg + $offset]" %}
-  interface(MEMORY_INTER) %{
-    base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
-    index(0xf); // PC => no index
-#endif
-    scale(0x0);
-    disp($offset);
-  %}
-%}
-
-// Indirect with Offset for half and double words
-operand indOffsetHD(sp_ptr_RegP reg, immIHD offset) %{
-  constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(AddP reg offset);
-
-  op_cost(100);
-  format %{ "[$reg + $offset]" %}
-  interface(MEMORY_INTER) %{
-    base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
-    index(0xf); // PC => no index
-#endif
-    scale(0x0);
-    disp($offset);
-  %}
-%}
-
-// Indirect with Offset and Offset+4 in ]-1024, 1024[
-operand indOffsetFPx2(sp_ptr_RegP reg, immX10x2 offset) %{
-  constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(AddP reg offset);
-
-  op_cost(100);
-  format %{ "[$reg + $offset]" %}
-  interface(MEMORY_INTER) %{
-    base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
-    index(0xf); // PC => no index
-#endif
-    scale(0x0);
-    disp($offset);
-  %}
-%}
-
-// Indirect with Offset and Offset+4 in ]-4096, 4096[
-operand indOffset12x2(sp_ptr_RegP reg, immI12x2 offset) %{
-  constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(AddP reg offset);
-
-  op_cost(100);
-  format %{ "[$reg + $offset]" %}
-  interface(MEMORY_INTER) %{
-    base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
-    index(0xf); // PC => no index
-#endif
-    scale(0x0);
-    disp($offset);
-  %}
-%}
-#endif // !AARCH64
-
 // Indirect with Register Index
 operand indIndex(iRegP addr, iRegX index) %{
   constraint(ALLOC_IN_RC(ptr_reg));
@@ -3019,9 +2585,8 @@
   %}
 %}
 
-#ifdef AARCH64
 // Indirect Memory Times Scale Plus Index Register
-operand indIndexScaleS(iRegP addr, iRegX index, immI_1 scale) %{
+operand indIndexScale(iRegP addr, iRegX index, immU5 scale) %{
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP addr (LShiftX index scale));
 
@@ -3035,127 +2600,6 @@
   %}
 %}
 
-// Indirect Memory Times Scale Plus 32-bit Index Register
-operand indIndexIScaleS(iRegP addr, iRegI index, immI_1 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX (ConvI2L index) scale));
-
-  op_cost(100);
-  format %{"[$addr + $index.w << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x7fffffff); // sxtw
-  %}
-%}
-
-// Indirect Memory Times Scale Plus Index Register
-operand indIndexScaleI(iRegP addr, iRegX index, immI_2 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX index scale));
-
-  op_cost(100);
-  format %{"[$addr + $index << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x0);
-  %}
-%}
-
-// Indirect Memory Times Scale Plus 32-bit Index Register
-operand indIndexIScaleI(iRegP addr, iRegI index, immI_2 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX (ConvI2L index) scale));
-
-  op_cost(100);
-  format %{"[$addr + $index.w << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x7fffffff); // sxtw
-  %}
-%}
-
-// Indirect Memory Times Scale Plus Index Register
-operand indIndexScaleL(iRegP addr, iRegX index, immI_3 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX index scale));
-
-  op_cost(100);
-  format %{"[$addr + $index << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x0);
-  %}
-%}
-
-// Indirect Memory Times Scale Plus 32-bit Index Register
-operand indIndexIScaleL(iRegP addr, iRegI index, immI_3 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX (ConvI2L index) scale));
-
-  op_cost(100);
-  format %{"[$addr + $index.w << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x7fffffff); // sxtw
-  %}
-%}
-
-// Indirect Memory Times Scale Plus Index Register
-operand indIndexScaleQ(iRegP addr, iRegX index, immI_4 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX index scale));
-
-  op_cost(100);
-  format %{"[$addr + $index << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x0);
-  %}
-%}
-
-// Indirect Memory Times Scale Plus 32-bit Index Register
-operand indIndexIScaleQ(iRegP addr, iRegI index, immI_4 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX (ConvI2L index) scale));
-
-  op_cost(100);
-  format %{"[$addr + $index.w << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x7fffffff); // sxtw
-  %}
-%}
-#else
-// Indirect Memory Times Scale Plus Index Register
-operand indIndexScale(iRegP addr, iRegX index, immU5 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX index scale));
-
-  op_cost(100);
-  format %{"[$addr + $index << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x0);
-  %}
-%}
-#endif
-
 // Operands for expressing Control Flow
 // NOTE:  Label is a predefined operand which should not be redefined in
 //        the AD file.  It is generically handled within the ADLC.
@@ -3312,29 +2756,6 @@
 // instructions for every form of operand when the instruction accepts
 // multiple operand types with the same basic encoding and format.  The classic
 // case of this is memory operands.
-#ifdef AARCH64
-opclass memoryB(indirect, indIndex, indOffsetU12ScaleB);
-opclass memoryS(indirect, indIndex, indIndexScaleS, indIndexIScaleS, indOffsetU12ScaleS);
-opclass memoryI(indirect, indIndex, indIndexScaleI, indIndexIScaleI, indOffsetU12ScaleI);
-opclass memoryL(indirect, indIndex, indIndexScaleL, indIndexIScaleL, indOffsetU12ScaleL);
-opclass memoryP(indirect, indIndex, indIndexScaleL, indIndexIScaleL, indOffsetU12ScaleL);
-opclass memoryQ(indirect, indIndex, indIndexScaleQ, indIndexIScaleQ, indOffsetU12ScaleQ);
-opclass memoryF(indirect, indIndex, indIndexScaleI, indIndexIScaleI, indOffsetU12ScaleI);
-opclass memoryD(indirect, indIndex, indIndexScaleL, indIndexIScaleL, indOffsetU12ScaleL);
-
-opclass memoryScaledS(indIndexScaleS, indIndexIScaleS);
-opclass memoryScaledI(indIndexScaleI, indIndexIScaleI);
-opclass memoryScaledL(indIndexScaleL, indIndexIScaleL);
-opclass memoryScaledP(indIndexScaleL, indIndexIScaleL);
-opclass memoryScaledQ(indIndexScaleQ, indIndexIScaleQ);
-opclass memoryScaledF(indIndexScaleI, indIndexIScaleI);
-opclass memoryScaledD(indIndexScaleL, indIndexIScaleL);
-// when ldrex/strex is used:
-opclass memoryex ( indirect );
-opclass indIndexMemory( indIndex );
-opclass memoryvld ( indirect /* , write back mode not implemented */ );
-
-#else
 
 opclass memoryI ( indirect, indOffset12, indIndex, indIndexScale );
 opclass memoryP ( indirect, indOffset12, indIndex, indIndexScale );
@@ -3354,7 +2775,6 @@
 opclass indIndexMemory( indIndex );
 opclass memorylong ( indirect, indOffset12x2 );
 opclass memoryvld ( indirect /* , write back mode not implemented */ );
-#endif
 
 //----------PIPELINE-----------------------------------------------------------
 pipeline %{
@@ -4163,7 +3583,6 @@
   size(4);
   format %{ "LDRSB   $dst,$mem\t! byte -> int" %}
   ins_encode %{
-    // High 32 bits are harmlessly set on Aarch64
     __ ldrsb($dst$$Register, $mem$$Address);
   %}
   ins_pipe(iload_mask_mem);
@@ -4174,13 +3593,6 @@
   match(Set dst (ConvI2L (LoadB mem)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRSB $dst,$mem\t! byte -> long"  %}
-  ins_encode %{
-    __ ldrsb($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRSB $dst.lo,$mem\t! byte -> long\n\t"
             "ASR   $dst.hi,$dst.lo,31" %}
@@ -4188,7 +3600,6 @@
     __ ldrsb($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), AsmOperand($dst$$Register, asr, 31));
   %}
-#endif
   ins_pipe(iload_mask_mem);
 %}
 
@@ -4210,13 +3621,6 @@
   match(Set dst (ConvI2L (LoadUB mem)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRB  $dst,$mem\t! ubyte -> long"  %}
-  ins_encode %{
-    __ ldrb($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRB  $dst.lo,$mem\t! ubyte -> long\n\t"
             "MOV   $dst.hi,0" %}
@@ -4224,7 +3628,6 @@
     __ ldrb($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
@@ -4232,16 +3635,6 @@
 instruct loadUB2L_limmI(iRegL dst, memoryB mem, limmIlow8 mask) %{
   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
 
-#ifdef AARCH64
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST);
-  size(8);
-  format %{ "LDRB  $dst,$mem\t! ubyte -> long\n\t"
-            "AND  $dst,$dst,$mask" %}
-  ins_encode %{
-    __ ldrb($dst$$Register, $mem$$Address);
-    __ andr($dst$$Register, $dst$$Register, limmI_low($mask$$constant, 8));
-  %}
-#else
   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
   size(12);
   format %{ "LDRB  $dst.lo,$mem\t! ubyte -> long\n\t"
@@ -4252,29 +3645,10 @@
     __ mov($dst$$Register->successor(), 0);
     __ andr($dst$$Register, $dst$$Register, limmI_low($mask$$constant, 8));
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
 // Load Short (16bit signed)
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadSoff(iRegI dst, memoryScaledS mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadS (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "LDRSH   $dst,$mem+$off\t! short temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldrsh($dst$$Register, nmem);
-  %}
-  ins_pipe(iload_mask_mem);
-%}
-#endif
 
 instruct loadS(iRegI dst, memoryS mem) %{
   match(Set dst (LoadS mem));
@@ -4297,7 +3671,6 @@
 
   format %{ "LDRSB   $dst,$mem\t! short -> byte" %}
   ins_encode %{
-    // High 32 bits are harmlessly set on Aarch64
     __ ldrsb($dst$$Register, $mem$$Address);
   %}
   ins_pipe(iload_mask_mem);
@@ -4308,13 +3681,6 @@
   match(Set dst (ConvI2L (LoadS mem)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRSH $dst,$mem\t! short -> long"  %}
-  ins_encode %{
-    __ ldrsh($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRSH $dst.lo,$mem\t! short -> long\n\t"
             "ASR   $dst.hi,$dst.lo,31" %}
@@ -4322,30 +3688,11 @@
     __ ldrsh($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), AsmOperand($dst$$Register, asr, 31));
   %}
-#endif
   ins_pipe(iload_mask_mem);
 %}
 
 // Load Unsigned Short/Char (16bit UNsigned)
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadUSoff(iRegI dst, memoryScaledS mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadUS (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "LDRH   $dst,$mem+$off\t! ushort/char temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldrh($dst$$Register, nmem);
-  %}
-  ins_pipe(iload_mem);
-%}
-#endif
 
 instruct loadUS(iRegI dst, memoryS mem) %{
   match(Set dst (LoadUS mem));
@@ -4377,13 +3724,6 @@
   match(Set dst (ConvI2L (LoadUS mem)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRH  $dst,$mem\t! short -> long"  %}
-  ins_encode %{
-    __ ldrh($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRH  $dst.lo,$mem\t! short -> long\n\t"
             "MOV   $dst.hi, 0" %}
@@ -4391,7 +3731,6 @@
     __ ldrh($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
@@ -4400,13 +3739,6 @@
   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRB  $dst,$mem"  %}
-  ins_encode %{
-    __ ldrb($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRB  $dst.lo,$mem\t! \n\t"
             "MOV   $dst.hi, 0" %}
@@ -4414,24 +3746,12 @@
     __ ldrb($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
 // Load Unsigned Short/Char (16bit UNsigned) with a immediate mask into a Long Register
 instruct loadUS2L_limmI(iRegL dst, memoryS mem, limmI mask) %{
   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
-#ifdef AARCH64
-  ins_cost(MEMORY_REF_COST + 1*DEFAULT_COST);
-
-  size(8);
-  format %{ "LDRH   $dst,$mem\t! ushort/char & mask -> long\n\t"
-            "AND    $dst,$dst,$mask" %}
-  ins_encode %{
-    __ ldrh($dst$$Register, $mem$$Address);
-    __ andr($dst$$Register, $dst$$Register, (uintx)$mask$$constant);
-  %}
-#else
   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
 
   size(12);
@@ -4443,30 +3763,11 @@
     __ mov($dst$$Register->successor(), 0);
     __ andr($dst$$Register, $dst$$Register, $mask$$constant);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
 // Load Integer
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadIoff(iRegI dst, memoryScaledI mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadI (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "ldr_s32 $dst,$mem+$off\t! int temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldr_s32($dst$$Register, nmem);
-  %}
-  ins_pipe(iload_mem);
-%}
-#endif
 
 instruct loadI(iRegI dst, memoryI mem) %{
   match(Set dst (LoadI mem));
@@ -4537,15 +3838,6 @@
 // Load Integer into a Long Register
 instruct loadI2L(iRegL dst, memoryI mem) %{
   match(Set dst (ConvI2L (LoadI mem)));
-#ifdef AARCH64
-  ins_cost(MEMORY_REF_COST);
-
-  size(4);
-  format %{ "LDRSW $dst.lo,$mem\t! int -> long"  %}
-  ins_encode %{
-    __ ldr_s32($dst$$Register, $mem$$Address);
-  %}
-#else
   ins_cost(MEMORY_REF_COST);
 
   size(8);
@@ -4555,22 +3847,12 @@
     __ ldr($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), AsmOperand($dst$$Register, asr, 31));
   %}
-#endif
   ins_pipe(iload_mask_mem);
 %}
 
 // Load Integer with mask 0xFF into a Long Register
 instruct loadI2L_immI_255(iRegL dst, memoryB mem, immI_255 mask) %{
   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
-#ifdef AARCH64
-  ins_cost(MEMORY_REF_COST);
-
-  size(4);
-  format %{ "LDRB   $dst.lo,$mem\t! int & 0xFF -> long"  %}
-  ins_encode %{
-    __ ldrb($dst$$Register, $mem$$Address);
-  %}
-#else
   ins_cost(MEMORY_REF_COST);
 
   size(8);
@@ -4580,7 +3862,6 @@
     __ ldrb($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
@@ -4589,13 +3870,6 @@
   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRH   $dst,$mem\t! int & 0xFFFF -> long" %}
-  ins_encode %{
-    __ ldrh($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRH   $dst,$mem\t! int & 0xFFFF -> long\n\t"
             "MOV    $dst.hi, 0" %}
@@ -4603,27 +3877,9 @@
     __ ldrh($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mask_mem);
 %}
 
-#ifdef AARCH64
-// Load Integer with an immediate mask into a Long Register
-instruct loadI2L_limmI(iRegL dst, memoryI mem, limmI mask) %{
-  match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
-  ins_cost(MEMORY_REF_COST + 1*DEFAULT_COST);
-
-  size(8);
-  format %{ "LDRSW $dst,$mem\t! int -> long\n\t"
-            "AND   $dst,$dst,$mask" %}
-
-  ins_encode %{
-    __ ldr_s32($dst$$Register, $mem$$Address);
-    __ andr($dst$$Register, $dst$$Register, (uintx)$mask$$constant);
-  %}
-  ins_pipe(iload_mem);
-%}
-#else
 // Load Integer with a 31-bit immediate mask into a Long Register
 instruct loadI2L_limmU31(iRegL dst, memoryI mem, limmU31 mask) %{
   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
@@ -4641,27 +3897,7 @@
   %}
   ins_pipe(iload_mem);
 %}
-#endif
-
-#ifdef AARCH64
-// Load Integer with mask into a Long Register
-// FIXME: use signedRegI mask, remove tmp?
-instruct loadI2L_immI(iRegL dst, memoryI mem, immI mask, iRegI tmp) %{
-  match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
-  effect(TEMP dst, TEMP tmp);
-
-  ins_cost(MEMORY_REF_COST + 3*DEFAULT_COST);
-  format %{ "LDRSW    $mem,$dst\t! int & 31-bit mask -> long\n\t"
-            "MOV_SLOW $tmp,$mask\n\t"
-            "AND      $dst,$tmp,$dst" %}
-  ins_encode %{
-    __ ldrsw($dst$$Register, $mem$$Address);
-    __ mov_slow($tmp$$Register, $mask$$constant);
-    __ andr($dst$$Register, $dst$$Register, $tmp$$Register);
-  %}
-  ins_pipe(iload_mem);
-%}
-#else
+
 // Load Integer with a 31-bit mask into a Long Register
 // FIXME: use iRegI mask, remove tmp?
 instruct loadI2L_immU31(iRegL dst, memoryI mem, immU31 mask, iRegI tmp) %{
@@ -4682,20 +3918,12 @@
   %}
   ins_pipe(iload_mem);
 %}
-#endif
 
 // Load Unsigned Integer into a Long Register
 instruct loadUI2L(iRegL dst, memoryI mem, immL_32bits mask) %{
   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-//size(4);
-  format %{ "LDR_w $dst,$mem\t! uint -> long" %}
-  ins_encode %{
-    __ ldr_w($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDR   $dst.lo,$mem\t! uint -> long\n\t"
             "MOV   $dst.hi,0" %}
@@ -4703,37 +3931,14 @@
     __ ldr($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
 // Load Long
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadLoff(iRegLd dst, memoryScaledL mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadL (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "LDR    $dst,$mem+$off\t! long temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldr($dst$$Register, nmem);
-  %}
-  ins_pipe(iload_mem);
-%}
-#endif
 
 instruct loadL(iRegLd dst, memoryL mem ) %{
-#ifdef AARCH64
-  // already atomic for Aarch64
-#else
   predicate(!((LoadLNode*)n)->require_atomic_access());
-#endif
   match(Set dst (LoadL mem));
   effect(TEMP dst);
   ins_cost(MEMORY_REF_COST);
@@ -4746,7 +3951,6 @@
   ins_pipe(iload_mem);
 %}
 
-#ifndef AARCH64
 instruct loadL_2instr(iRegL dst, memorylong mem ) %{
   predicate(!((LoadLNode*)n)->require_atomic_access());
   match(Set dst (LoadL mem));
@@ -4822,7 +4026,6 @@
   %}
   ins_pipe(iload_mem);
 %}
-#endif // !AARCH64
 
 // Load Range
 instruct loadRange(iRegI dst, memoryI mem) %{
@@ -4839,24 +4042,6 @@
 
 // Load Pointer
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadPoff(iRegP dst, memoryScaledP mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadP (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "LDR    $dst,$mem+$off\t! ptr temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldr($dst$$Register, nmem);
-  %}
-  ins_pipe(iload_mem);
-%}
-#endif
 
 instruct loadP(iRegP dst, memoryP mem) %{
   match(Set dst (LoadP mem));
@@ -4950,24 +4135,6 @@
 %}
 #endif
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadDoff(regD dst, memoryScaledD mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadD (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "ldr    $dst,$mem+$off\t! double temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldr_d($dst$$FloatRegister, nmem);
-  %}
-  ins_pipe(floadD_mem);
-%}
-#endif
 
 instruct loadD(regD dst, memoryD mem) %{
   match(Set dst (LoadD mem));
@@ -4983,7 +4150,6 @@
   ins_pipe(floadD_mem);
 %}
 
-#ifndef AARCH64
 // Load Double - UNaligned
 instruct loadD_unaligned(regD_low dst, memoryF2 mem ) %{
   match(Set dst (LoadD_unaligned mem));
@@ -4999,26 +4165,7 @@
   %}
   ins_pipe(iload_mem);
 %}
-#endif
-
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadFoff(regF dst, memoryScaledF mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadF (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "ldr    $dst,$mem+$off\t! float temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldr_s($dst$$FloatRegister, nmem);
-  %}
-  ins_pipe(floadF_mem);
-%}
-#endif
+
 
 instruct loadF(regF dst, memoryF mem) %{
   match(Set dst (LoadF mem));
@@ -5032,17 +4179,6 @@
   ins_pipe(floadF_mem);
 %}
 
-#ifdef AARCH64
-instruct load_limmI(iRegI dst, limmI src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST + 1); // + 1 because MOV is preferred
-  format %{ "ORR_w  $dst, ZR, $src\t! int"  %}
-  ins_encode %{
-    __ orr_w($dst$$Register, ZR, (uintx)$src$$constant);
-  %}
-  ins_pipe(ialu_imm);
-%}
-#endif
 
 // // Load Constant
 instruct loadConI( iRegI dst, immI src ) %{
@@ -5065,7 +4201,6 @@
   ins_pipe(ialu_imm);
 %}
 
-#ifndef AARCH64
 instruct loadConIMovn( iRegI dst, immIRotn src ) %{
   match(Set dst src);
   size(4);
@@ -5075,22 +4210,13 @@
   %}
   ins_pipe(ialu_imm_n);
 %}
-#endif
 
 instruct loadConI16( iRegI dst, immI16 src ) %{
   match(Set dst src);
   size(4);
-#ifdef AARCH64
-  format %{ "MOVZ_w  $dst, $src" %}
-#else
   format %{ "MOVW    $dst, $src" %}
-#endif
-  ins_encode %{
-#ifdef AARCH64
-    __ mov_w($dst$$Register, $src$$constant);
-#else
+  ins_encode %{
     __ movw($dst$$Register, $src$$constant);
-#endif
   %}
   ins_pipe(ialu_imm_n);
 %}
@@ -5124,80 +4250,6 @@
   ins_pipe(loadConP_poll);
 %}
 
-#ifdef AARCH64
-instruct loadConP0(iRegP dst, immP0 src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST);
-  format %{ "MOV    $dst,ZR\t!ptr" %}
-  ins_encode %{
-    __ mov($dst$$Register, ZR);
-  %}
-  ins_pipe(ialu_none);
-%}
-
-instruct loadConN(iRegN dst, immN src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST * 3/2);
-  format %{ "SET    $dst,$src\t! compressed ptr" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    // FIXME: use $constanttablebase?
-    __ set_narrow_oop(dst, (jobject)$src$$constant);
-  %}
-  ins_pipe(ialu_hi_lo_reg);
-%}
-
-instruct loadConN0(iRegN dst, immN0 src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST);
-  format %{ "MOV    $dst,ZR\t! compressed ptr" %}
-  ins_encode %{
-    __ mov($dst$$Register, ZR);
-  %}
-  ins_pipe(ialu_none);
-%}
-
-instruct loadConNKlass(iRegN dst, immNKlass src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST * 3/2);
-  format %{ "SET    $dst,$src\t! compressed klass ptr" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    // FIXME: use $constanttablebase?
-    __ set_narrow_klass(dst, (Klass*)$src$$constant);
-  %}
-  ins_pipe(ialu_hi_lo_reg);
-%}
-
-instruct load_limmL(iRegL dst, limmL src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST);
-  format %{ "ORR    $dst, ZR, $src\t! long"  %}
-  ins_encode %{
-    __ orr($dst$$Register, ZR, (uintx)$src$$constant);
-  %}
-  ins_pipe(loadConL);
-%}
-instruct load_immLMov(iRegL dst, immLMov src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST);
-  format %{ "MOV    $dst, $src\t! long"  %}
-  ins_encode %{
-    __ mov($dst$$Register, $src$$constant);
-  %}
-  ins_pipe(loadConL);
-%}
-instruct loadConL(iRegL dst, immL src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST * 4); // worst case
-  format %{ "mov_slow   $dst, $src\t! long"  %}
-  ins_encode %{
-    // FIXME: use $constanttablebase?
-    __ mov_slow($dst$$Register, $src$$constant);
-  %}
-  ins_pipe(loadConL);
-%}
-#else
 instruct loadConL(iRegL dst, immL src) %{
   match(Set dst src);
   ins_cost(DEFAULT_COST * 4);
@@ -5223,7 +4275,6 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif
 
 instruct loadConF_imm8(regF dst, imm8F src) %{
   match(Set dst src);
@@ -5238,25 +4289,6 @@
   ins_pipe(loadConFD); // FIXME
 %}
 
-#ifdef AARCH64
-instruct loadIConF(iRegI dst, immF src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST * 2);
-
-  format %{ "MOV_SLOW  $dst, $src\t! loadIConF"  %}
-
-  ins_encode %{
-    // FIXME revisit once 6961697 is in
-    union {
-      jfloat f;
-      int i;
-    } v;
-    v.f = $src$$constant;
-    __ mov_slow($dst$$Register, v.i);
-  %}
-  ins_pipe(ialu_imm);
-%}
-#endif
 
 instruct loadConF(regF dst, immF src, iRegI tmp) %{
   match(Set dst src);
@@ -5323,11 +4355,7 @@
 
   format %{ "PLDW $mem\t! Prefetch allocation" %}
   ins_encode %{
-#ifdef AARCH64
-    __ prfm(pstl1keep, $mem$$Address);
-#else
     __ pldw($mem$$Address);
-#endif
   %}
   ins_pipe(iload_mem);
 %}
@@ -5360,24 +4388,6 @@
 
 // Store Char/Short
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeCoff(store_RegI src, memoryScaledS mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreC (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "STRH    $src,$mem+$off\t! short temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ strh($src$$Register, nmem);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 instruct storeC(memoryS mem, store_RegI src) %{
   match(Set mem (StoreC mem src));
@@ -5393,24 +4403,6 @@
 
 // Store Integer
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeIoff(store_RegI src, memoryScaledI mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreI (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "str_32 $src,$mem+$off\t! int temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str_32($src$$Register, nmem);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 instruct storeI(memoryI mem, store_RegI src) %{
   match(Set mem (StoreI mem src));
@@ -5426,31 +4418,9 @@
 
 // Store Long
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeLoff(store_RegLd src, memoryScaledL mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreL (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "str_64 $src,$mem+$off\t! long temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str_64($src$$Register, nmem);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 instruct storeL(memoryL mem, store_RegLd src) %{
-#ifdef AARCH64
-  // already atomic for Aarch64
-#else
   predicate(!((StoreLNode*)n)->require_atomic_access());
-#endif
   match(Set mem (StoreL mem src));
   ins_cost(MEMORY_REF_COST);
 
@@ -5463,7 +4433,6 @@
   ins_pipe(istore_mem_reg);
 %}
 
-#ifndef AARCH64
 instruct storeL_2instr(memorylong mem, iRegL src) %{
   predicate(!((StoreLNode*)n)->require_atomic_access());
   match(Set mem (StoreL mem src));
@@ -5496,9 +4465,7 @@
   %}
   ins_pipe(istore_mem_reg);
 %}
-#endif // !AARCH64
-
-#ifndef AARCH64
+
 instruct storeL_volatile_fp(memoryD mem, iRegL src) %{
   predicate(((StoreLNode*)n)->require_atomic_access());
   match(Set mem (StoreL mem src));
@@ -5512,7 +4479,6 @@
   %}
   ins_pipe(istore_mem_reg);
 %}
-#endif
 
 #ifdef XXX
 // Move SP Pointer
@@ -5534,60 +4500,12 @@
 %}
 #endif
 
-#ifdef AARCH64
-// FIXME
-// Store SP Pointer
-instruct storeSP(memoryP mem, SPRegP src, iRegP tmp) %{
-  match(Set mem (StoreP mem src));
-  predicate(_kids[1]->_leaf->is_Proj() && _kids[1]->_leaf->as_Proj()->_con == TypeFunc::FramePtr);
-  // Multiple StoreP rules, different only in register mask.
-  // Matcher makes the last always valid.  The others will
-  // only be valid if they cost less than the last valid
-  // rule.  So cost(rule1) < cost(rule2) < cost(last)
-  // Unlike immediates, register constraints are not checked
-  // at match time.
-  ins_cost(MEMORY_REF_COST+DEFAULT_COST+4);
-  effect(TEMP tmp);
-  size(8);
-
-  format %{ "MOV    $tmp,$src\t! SP ptr\n\t"
-            "STR    $tmp,$mem\t! SP ptr" %}
-  ins_encode %{
-    assert($src$$Register == SP, "SP expected");
-    __ mov($tmp$$Register, $src$$Register);
-    __ str($tmp$$Register, $mem$$Address);
-  %}
-  ins_pipe(istore_mem_spORreg); // FIXME
-%}
-#endif // AARCH64
 
 // Store Pointer
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storePoff(store_ptr_RegP src, memoryScaledP mem, aimmX off, iRegP tmp) %{
-  predicate(!_kids[1]->_leaf->is_Proj() || _kids[1]->_leaf->as_Proj()->_con != TypeFunc::FramePtr);
-  match(Set mem (StoreP (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "STR    $src,$mem+$off\t! ptr temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str($src$$Register, nmem);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 instruct storeP(memoryP mem, store_ptr_RegP src) %{
   match(Set mem (StoreP mem src));
-#ifdef AARCH64
-  predicate(!_kids[1]->_leaf->is_Proj() || _kids[1]->_leaf->as_Proj()->_con != TypeFunc::FramePtr);
-#endif
   ins_cost(MEMORY_REF_COST);
   size(4);
 
@@ -5598,42 +4516,10 @@
   ins_pipe(istore_mem_spORreg);
 %}
 
-#ifdef AARCH64
-// Store NULL Pointer
-instruct storeP0(memoryP mem, immP0 src) %{
-  match(Set mem (StoreP mem src));
-  ins_cost(MEMORY_REF_COST);
-  size(4);
-
-  format %{ "STR    ZR,$mem\t! ptr" %}
-  ins_encode %{
-    __ str(ZR, $mem$$Address);
-  %}
-  ins_pipe(istore_mem_spORreg);
-%}
-#endif // AARCH64
 
 #ifdef _LP64
 // Store Compressed Pointer
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeNoff(store_RegN src, memoryScaledI mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreN (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "str_32 $src,$mem+$off\t! compressed ptr temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str_32($src$$Register, nmem);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 instruct storeN(memoryI mem, store_RegN src) %{
   match(Set mem (StoreN mem src));
@@ -5647,20 +4533,6 @@
   ins_pipe(istore_mem_reg);
 %}
 
-#ifdef AARCH64
-// Store NULL Pointer
-instruct storeN0(memoryI mem, immN0 src) %{
-  match(Set mem (StoreN mem src));
-  ins_cost(MEMORY_REF_COST);
-  size(4);
-
-  format %{ "str_32 ZR,$mem\t! compressed ptr" %}
-  ins_encode %{
-    __ str_32(ZR, $mem$$Address);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 // Store Compressed Klass Pointer
 instruct storeNKlass(memoryI mem, store_RegN src) %{
@@ -5678,24 +4550,6 @@
 
 // Store Double
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeDoff(regD src, memoryScaledD mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreD (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "STR    $src,$mem+$off\t! double temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str_d($src$$FloatRegister, nmem);
-  %}
-  ins_pipe(fstoreD_mem_reg);
-%}
-#endif
 
 instruct storeD(memoryD mem, regD src) %{
   match(Set mem (StoreD mem src));
@@ -5711,50 +4565,9 @@
   ins_pipe(fstoreD_mem_reg);
 %}
 
-#ifdef AARCH64
-instruct movI2F(regF dst, iRegI src) %{
-  match(Set dst src);
-  size(4);
-
-  format %{ "FMOV_sw $dst,$src\t! movI2F" %}
-  ins_encode %{
-    __ fmov_sw($dst$$FloatRegister, $src$$Register);
-  %}
-  ins_pipe(ialu_reg); // FIXME
-%}
-
-instruct movF2I(iRegI dst, regF src) %{
-  match(Set dst src);
-  size(4);
-
-  format %{ "FMOV_ws $dst,$src\t! movF2I" %}
-  ins_encode %{
-    __ fmov_ws($dst$$Register, $src$$FloatRegister);
-  %}
-  ins_pipe(ialu_reg); // FIXME
-%}
-#endif
 
 // Store Float
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeFoff(regF src, memoryScaledF mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreF (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "str_s  $src,$mem+$off\t! float temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str_s($src$$FloatRegister, nmem);
-  %}
-  ins_pipe(fstoreF_mem_reg);
-%}
-#endif
 
 instruct storeF( memoryF mem, regF src) %{
   match(Set mem (StoreF mem src));
@@ -5768,75 +4581,10 @@
   ins_pipe(fstoreF_mem_reg);
 %}
 
-#ifdef AARCH64
-// Convert oop pointer into compressed form
-instruct encodeHeapOop(iRegN dst, iRegP src, flagsReg ccr) %{
-  predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
-  match(Set dst (EncodeP src));
-  effect(KILL ccr);
-  format %{ "encode_heap_oop $dst, $src" %}
-  ins_encode %{
-    __ encode_heap_oop($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
-  predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
-  match(Set dst (EncodeP src));
-  format %{ "encode_heap_oop_not_null $dst, $src" %}
-  ins_encode %{
-    __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct decodeHeapOop(iRegP dst, iRegN src, flagsReg ccr) %{
-  predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
-            n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
-  match(Set dst (DecodeN src));
-  effect(KILL ccr);
-  format %{ "decode_heap_oop $dst, $src" %}
-  ins_encode %{
-    __ decode_heap_oop($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
-  predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
-            n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
-  match(Set dst (DecodeN src));
-  format %{ "decode_heap_oop_not_null $dst, $src" %}
-  ins_encode %{
-    __ decode_heap_oop_not_null($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
-  match(Set dst (EncodePKlass src));
-  format %{ "encode_klass_not_null $dst, $src" %}
-  ins_encode %{
-    __ encode_klass_not_null($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
-  match(Set dst (DecodeNKlass src));
-  format %{ "decode_klass_not_null $dst, $src" %}
-  ins_encode %{
-    __ decode_klass_not_null($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-#endif // AARCH64
 
 //----------MemBar Instructions-----------------------------------------------
 // Memory barrier flavors
 
-// TODO: take advantage of Aarch64 load-acquire, store-release, etc
 // pattern-match out unnecessary membars
 instruct membar_storestore() %{
   match(MemBarStoreStore);
@@ -5932,53 +4680,6 @@
 // %}
 
 
-#ifdef AARCH64
-// 0 constant in register
-instruct zrImmI0(ZRRegI dst, immI0 imm) %{
-  match(Set dst imm);
-  size(0);
-  ins_cost(0);
-
-  format %{ "! ZR (int 0)" %}
-  ins_encode( /*empty encoding*/ );
-  ins_pipe(ialu_none);
-%}
-
-// 0 constant in register
-instruct zrImmL0(ZRRegL dst, immL0 imm) %{
-  match(Set dst imm);
-  size(0);
-  ins_cost(0);
-
-  format %{ "! ZR (long 0)" %}
-  ins_encode( /*empty encoding*/ );
-  ins_pipe(ialu_none);
-%}
-
-#ifdef XXX
-// 0 constant in register
-instruct zrImmN0(ZRRegN dst, immN0 imm) %{
-  match(Set dst imm);
-  size(0);
-  ins_cost(0);
-
-  format %{ "! ZR (compressed pointer NULL)" %}
-  ins_encode( /*empty encoding*/ );
-  ins_pipe(ialu_none);
-%}
-
-// 0 constant in register
-instruct zrImmP0(ZRRegP dst, immP0 imm) %{
-  match(Set dst imm);
-  size(0);
-  ins_cost(0);
-
-  format %{ "! ZR (NULL)" %}
-  ins_encode( /*empty encoding*/ );
-  ins_pipe(ialu_none);
-%}
-#endif
-#endif // AARCH64
 
 // Cast Index to Pointer for unsafe natives
 instruct castX2P(iRegX src, iRegP dst) %{
@@ -6006,7 +4707,6 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifndef AARCH64
 //----------Conditional Move---------------------------------------------------
 // Conditional move
 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
@@ -6019,187 +4719,8 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif
-
-#ifdef AARCH64
-instruct cmovI_reg3(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src1, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! int" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovL_reg3(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! long" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovP_reg3(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src1, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovN_reg3(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src1, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! compressed ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovIP_reg3(cmpOpP cmp, flagsRegP icc, iRegI dst, iRegI src1, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! int" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovLP_reg3(cmpOpP cmp, flagsRegP icc, iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! long" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovPP_reg3(cmpOpP cmp, flagsRegP icc, iRegP dst, iRegP src1, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovNP_reg3(cmpOpP cmp, flagsRegP icc, iRegN dst, iRegN src1, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! compressed ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovIU_reg3(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src1, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! int" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovLU_reg3(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! long" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovPU_reg3(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src1, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovNU_reg3(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src1, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! compressed ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovIZ_reg3(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegI dst, iRegI src1, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! int" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovLZ_reg3(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! long" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovPZ_reg3(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegP dst, iRegP src1, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovNZ_reg3(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegN dst, iRegN src1, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! compressed ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-#endif // AARCH64
-
-#ifndef AARCH64
+
+
 instruct cmovIP_immMov(cmpOpP cmp, flagsRegP pcc, iRegI dst, immIMov src) %{
   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
   ins_cost(140);
@@ -6221,7 +4742,6 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif
 
 instruct cmovI_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
@@ -6234,20 +4754,7 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifdef AARCH64
-instruct cmovL_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
-  match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
-  ins_cost(150);
-  size(4);
-  format %{ "MOV$cmp  $dst,$src\t! long" %}
-  ins_encode %{
-    __ mov($dst$$Register, $src$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-#endif
-
-#ifndef AARCH64
+
 instruct cmovI_immMov(cmpOp cmp, flagsReg icc, iRegI dst, immIMov src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
   ins_cost(140);
@@ -6269,7 +4776,6 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif
 
 instruct cmovII_reg_EQNELTGE(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegI dst, iRegI src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
@@ -6286,7 +4792,6 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifndef AARCH64
 instruct cmovII_immMov_EQNELTGE(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegI dst, immIMov src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
   predicate(_kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq ||
@@ -6316,7 +4821,6 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif
 
 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
@@ -6329,7 +4833,6 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifndef AARCH64
 instruct cmovIIu_immMov(cmpOpU cmp, flagsRegU icc, iRegI dst, immIMov src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
   ins_cost(140);
@@ -6351,7 +4854,6 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif
 
 // Conditional move
 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
@@ -6369,17 +4871,9 @@
   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
   ins_cost(140);
   size(4);
-#ifdef AARCH64
-  format %{ "MOV$cmp  $dst,ZR" %}
-#else
   format %{ "MOV$cmp  $dst,$src" %}
-#endif
-  ins_encode %{
-#ifdef AARCH64
-    __ mov($dst$$Register,             ZR, (AsmCondition)($cmp$$cmpcode));
-#else
+  ins_encode %{
     __ mov($dst$$Register, $src$$constant, (AsmCondition)($cmp$$cmpcode));
-#endif
   %}
   ins_pipe(ialu_imm);
 %}
@@ -6430,17 +4924,9 @@
   ins_cost(140);
 
   size(4);
-#ifdef AARCH64
-  format %{ "MOV$cmp  $dst,ZR\t! ptr" %}
-#else
   format %{ "MOV$cmp  $dst,$src\t! ptr" %}
-#endif
-  ins_encode %{
-#ifdef AARCH64
-    __ mov($dst$$Register,             ZR, (AsmCondition)($cmp$$cmpcode));
-#else
+  ins_encode %{
     __ mov($dst$$Register, $src$$constant, (AsmCondition)($cmp$$cmpcode));
-#endif
   %}
   ins_pipe(ialu_imm);
 %}
@@ -6454,17 +4940,9 @@
   ins_cost(140);
 
   size(4);
-#ifdef AARCH64
-  format %{ "MOV$cmp  $dst,ZR\t! ptr" %}
-#else
   format %{ "MOV$cmp  $dst,$src\t! ptr" %}
-#endif
-  ins_encode %{
-#ifdef AARCH64
-    __ mov($dst$$Register,             ZR, (AsmCondition)($cmp$$cmpcode));
-#else
+  ins_encode %{
     __ mov($dst$$Register, $src$$constant, (AsmCondition)($cmp$$cmpcode));
-#endif
   %}
   ins_pipe(ialu_imm);
 %}
@@ -6474,112 +4952,13 @@
   ins_cost(140);
 
   size(4);
-#ifdef AARCH64
-  format %{ "MOV$cmp  $dst,ZR\t! ptr" %}
-#else
   format %{ "MOV$cmp  $dst,$src\t! ptr" %}
-#endif
-  ins_encode %{
-#ifdef AARCH64
-    __ mov($dst$$Register,             ZR, (AsmCondition)($cmp$$cmpcode));
-#else
+  ins_encode %{
     __ mov($dst$$Register, $src$$constant, (AsmCondition)($cmp$$cmpcode));
-#endif
   %}
   ins_pipe(ialu_imm);
 %}
 
-#ifdef AARCH64
-// Conditional move
-instruct cmovF_reg(cmpOp cmp, flagsReg icc, regF dst, regF src1, regF src2) %{
-  match(Set dst (CMoveF (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_s $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovD_reg(cmpOp cmp, flagsReg icc, regD dst, regD src1, regD src2) %{
-  match(Set dst (CMoveD (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_d $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_d($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovFP_reg(cmpOpP cmp, flagsRegP icc, regF dst, regF src1, regF src2) %{
-  match(Set dst (CMoveF (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_s $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovDP_reg(cmpOpP cmp, flagsRegP icc, regD dst, regD src1, regD src2) %{
-  match(Set dst (CMoveD (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_d $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_d($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovFU_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src1, regF src2) %{
-  match(Set dst (CMoveF (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_s $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovDU_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src1, regD src2) %{
-  match(Set dst (CMoveD (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_d $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_d($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovFZ_reg(cmpOp0 cmp, flagsReg_EQNELTGE icc, regF dst, regF src1, regF src2) %{
-  match(Set dst (CMoveF (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_s $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovDZ_reg(cmpOp0 cmp, flagsReg_EQNELTGE icc, regD dst, regD src1, regD src2) %{
-  match(Set dst (CMoveD (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_d $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_d($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-#else // !AARCH64
 
 // Conditional move
 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
@@ -6840,7 +5219,6 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif // !AARCH64
 
 
 //----------OS and Locking Instructions----------------------------------------
@@ -6897,7 +5275,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct addshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AddI (LShiftI src1 src2) src3));
 
@@ -6908,22 +5285,7 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
-
-#ifdef AARCH64
-#ifdef TODO
-instruct addshlL_reg_imm_reg(iRegL dst, iRegL src1, immU6 src2, iRegL src3) %{
-  match(Set dst (AddL (LShiftL src1 src2) src3));
-
-  size(4);
-  format %{ "ADD    $dst,$src3,$src1<<$src2\t! long" %}
-  ins_encode %{
-    __ add($dst$$Register, $src3$$Register, AsmOperand($src1$$Register, lsl, $src2$$constant));
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-#endif
-#endif
+
 
 instruct addshlI_reg_imm_reg(iRegI dst, iRegI src1, immU5 src2, iRegI src3) %{
   match(Set dst (AddI (LShiftI src1 src2) src3));
@@ -6936,7 +5298,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct addsarI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AddI (RShiftI src1 src2) src3));
 
@@ -6947,7 +5308,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct addsarI_reg_imm_reg(iRegI dst, iRegI src1, immU5 src2, iRegI src3) %{
   match(Set dst (AddI (RShiftI src1 src2) src3));
@@ -6960,7 +5320,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct addshrI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AddI (URShiftI src1 src2) src3));
 
@@ -6971,7 +5330,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct addshrI_reg_imm_reg(iRegI dst, iRegI src1, immU5 src2, iRegI src3) %{
   match(Set dst (AddI (URShiftI src1 src2) src3));
@@ -7008,69 +5366,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifdef AARCH64
-// unshifted I2L operand
-operand unshiftedI2L(iRegI src2) %{
-//constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(ConvI2L src2);
-
-  op_cost(1);
-  format %{ "$src2.w" %}
-  interface(MEMORY_INTER) %{
-    base($src2);
-    index(0xff);
-    scale(0x0);
-    disp(0x0);
-  %}
-%}
-
-// shifted I2L operand
-operand shiftedI2L(iRegI src2, immI_0_4 src3) %{
-//constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(LShiftX (ConvI2L src2) src3);
-
-  op_cost(1);
-  format %{ "$src2.w << $src3" %}
-  interface(MEMORY_INTER) %{
-    base($src2);
-    index(0xff);
-    scale($src3);
-    disp(0x0);
-  %}
-%}
-
-opclass shiftedRegI(shiftedI2L, unshiftedI2L);
-
-instruct shlL_reg_regI(iRegL dst, iRegI src1, immU6 src2) %{
-  match(Set dst (LShiftL (ConvI2L src1) src2));
-
-  size(4);
-  format %{ "LSL    $dst,$src1.w,$src2\t! ptr" %}
-  ins_encode %{
-    int c = $src2$$constant;
-    int r = 64 - c;
-    int s = 31;
-    if (s >= r) {
-      s = r - 1;
-    }
-    __ sbfm($dst$$Register, $src1$$Register, r, s);
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-
-instruct addP_reg_regI(iRegP dst, iRegP src1, shiftedRegI src2) %{
-  match(Set dst (AddP src1 src2));
-
-  ins_cost(DEFAULT_COST * 3/2);
-  size(4);
-  format %{ "ADD    $dst,$src1,$src2, sxtw\t! ptr" %}
-  ins_encode %{
-    Register base = reg_to_register_object($src2$$base);
-    __ add($dst$$Register, $src1$$Register, base, ex_sxtw, $src2$$scale);
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-#endif
 
 // shifted iRegX operand
 operand shiftedX(iRegX src2, shimmX src3) %{
@@ -7113,30 +5408,6 @@
 %}
 
 // Long Addition
-#ifdef AARCH64
-instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (AddL src1 src2));
-  size(4);
-  format %{ "ADD     $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ add($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-
-instruct addL_reg_regI(iRegL dst, iRegL src1, shiftedRegI src2) %{
-  match(Set dst (AddL src1 src2));
-
-  ins_cost(DEFAULT_COST * 3/2);
-  size(4);
-  format %{ "ADD    $dst,$src1,$src2, sxtw\t! long" %}
-  ins_encode %{
-    Register base = reg_to_register_object($src2$$base);
-    __ add($dst$$Register, $src1$$Register, base, ex_sxtw, $src2$$scale);
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-#else
 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2, flagsReg ccr) %{
   match(Set dst (AddL src1 src2));
   effect(KILL ccr);
@@ -7149,36 +5420,9 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
-
-#ifdef AARCH64
-// Immediate Addition
-instruct addL_reg_aimm(iRegL dst, iRegL src1, aimmL src2) %{
-  match(Set dst (AddL src1 src2));
-
-  size(4);
-  format %{ "ADD    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ add($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-
-instruct addL_reg_immLneg(iRegL dst, iRegL src1, aimmLneg src2) %{
-  match(Set dst (SubL src1 src2));
-
-  size(4);
-  format %{ "ADD    $dst,$src1,-($src2)\t! long" %}
-  ins_encode %{
-    __ add($dst$$Register, $src1$$Register, -$src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
+
 // TODO
-#endif
-
-#ifndef AARCH64
+
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct addL_reg_immRot(iRegL dst, iRegL src1, immLlowRot con, flagsReg ccr) %{
@@ -7193,26 +5437,19 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 //----------Conditional_store--------------------------------------------------
 // Conditional-store of the updated heap-top.
 // Used during allocation of the shared heap.
 // Sets flags (EQ) on success.
 
-// TODO: optimize out barriers with AArch64 load-acquire/store-release
 // LoadP-locked.
 instruct loadPLocked(iRegP dst, memoryex mem) %{
   match(Set dst (LoadPLocked mem));
   size(4);
   format %{ "LDREX  $dst,$mem" %}
   ins_encode %{
-#ifdef AARCH64
-    Register base = reg_to_register_object($mem$$base);
-    __ ldxr($dst$$Register, base);
-#else
     __ ldrex($dst$$Register,$mem$$Address);
-#endif
   %}
   ins_pipe(iload_mem);
 %}
@@ -7225,12 +5462,7 @@
   format %{ "STREX  $tmp,$newval,$heap_top_ptr\n\t"
             "CMP    $tmp, 0" %}
   ins_encode %{
-#ifdef AARCH64
-    Register base = reg_to_register_object($heap_top_ptr$$base);
-    __ stxr($tmp$$Register, $newval$$Register, base);
-#else
     __ strex($tmp$$Register, $newval$$Register, $heap_top_ptr$$Address);
-#endif
     __ cmp($tmp$$Register, 0);
   %}
   ins_pipe( long_memory_op );
@@ -7238,20 +5470,6 @@
 
 // Conditional-store of an intx value.
 instruct storeXConditional( memoryex mem, iRegX oldval, iRegX newval, iRegX tmp, flagsReg icc ) %{
-#ifdef AARCH64
-  match(Set icc (StoreLConditional mem (Binary oldval newval)));
-  effect( TEMP tmp );
-  size(28);
-  format %{ "loop:\n\t"
-            "LDXR     $tmp, $mem\t! If $oldval==[$mem] Then store $newval into [$mem], DOESN'T set $newval=[$mem] in any case\n\t"
-            "SUBS     $tmp, $tmp, $oldval\n\t"
-            "B.ne     done\n\t"
-            "STXR     $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop\n\t"
-            "CMP      $tmp, 0\n\t"
-            "done:\n\t"
-            "membar   LoadStore|LoadLoad" %}
-#else
   match(Set icc (StoreIConditional mem (Binary oldval newval)));
   effect( TEMP tmp );
   size(28);
@@ -7263,29 +5481,15 @@
             "B.eq     loop \n\t"
             "TEQ      $tmp, 0\n\t"
             "membar   LoadStore|LoadLoad" %}
-#endif
   ins_encode %{
     Label loop;
     __ bind(loop);
-#ifdef AARCH64
-// FIXME: use load-acquire/store-release, remove membar?
-    Label done;
-    Register base = reg_to_register_object($mem$$base);
-    __ ldxr($tmp$$Register, base);
-    __ subs($tmp$$Register, $tmp$$Register, $oldval$$Register);
-    __ b(done, ne);
-    __ stxr($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-    __ cmp($tmp$$Register, 0);
-    __ bind(done);
-#else
     __ ldrex($tmp$$Register, $mem$$Address);
     __ eors($tmp$$Register, $tmp$$Register, $oldval$$Register);
     __ strex($tmp$$Register, $newval$$Register, $mem$$Address, eq);
     __ cmp($tmp$$Register, 1, eq);
     __ b(loop, eq);
     __ teq($tmp$$Register, 0);
-#endif
     // used by biased locking only. Requires a membar.
     __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadStore | MacroAssembler::LoadLoad), noreg);
   %}
@@ -7294,118 +5498,6 @@
 
 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
 
-#ifdef AARCH64
-// TODO: if combined with membar, elide membar and use
-// load-acquire/store-release if appropriate
-instruct compareAndSwapL_bool(memoryex mem, iRegL oldval, iRegL newval, iRegI res, iRegI tmp, flagsReg ccr) %{
-  match(Set res (CompareAndSwapL mem (Binary oldval newval)));
-  effect( KILL ccr, TEMP tmp);
-  size(24);
-  format %{ "loop:\n\t"
-            "LDXR     $tmp, $mem\t! If $oldval==[$mem] Then store $newval into [$mem]\n\t"
-            "CMP      $tmp, $oldval\n\t"
-            "B.ne     done\n\t"
-            "STXR     $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop\n\t"
-            "done:\n\t"
-            "CSET_w   $res, eq" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    Label loop, done;
-    __ bind(loop);
-    __ ldxr($tmp$$Register, base);
-    __ cmp($tmp$$Register, $oldval$$Register);
-    __ b(done, ne);
-    __ stxr($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-    __ bind(done);
-    __ cset_w($res$$Register, eq);
-  %}
-  ins_pipe( long_memory_op );
-%}
-
-instruct compareAndSwapI_bool(memoryex mem, iRegI oldval, iRegI newval, iRegI res, iRegI tmp, flagsReg ccr) %{
-  match(Set res (CompareAndSwapI mem (Binary oldval newval)));
-  effect( KILL ccr, TEMP tmp);
-  size(24);
-  format %{ "loop:\n\t"
-            "LDXR_w   $tmp, $mem\t! If $oldval==[$mem] Then store $newval into [$mem]\n\t"
-            "CMP_w    $tmp, $oldval\n\t"
-            "B.ne     done\n\t"
-            "STXR_w   $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop\n\t"
-            "done:\n\t"
-            "CSET_w   $res, eq" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    Label loop, done;
-    __ bind(loop);
-    __ ldxr_w($tmp$$Register, base);
-    __ cmp_w($tmp$$Register, $oldval$$Register);
-    __ b(done, ne);
-    __ stxr_w($tmp$$Register, $newval$$Register,  base);
-    __ cbnz_w($tmp$$Register, loop);
-    __ bind(done);
-    __ cset_w($res$$Register, eq);
-  %}
-  ins_pipe( long_memory_op );
-%}
-
-// tmp must use iRegI instead of iRegN until 8051805 is fixed.
-instruct compareAndSwapN_bool(memoryex mem, iRegN oldval, iRegN newval, iRegI res, iRegI tmp, flagsReg ccr) %{
-  match(Set res (CompareAndSwapN mem (Binary oldval newval)));
-  effect( KILL ccr, TEMP tmp);
-  size(24);
-  format %{ "loop:\n\t"
-            "LDXR_w   $tmp, $mem\t! If $oldval==[$mem] Then store $newval into [$mem]\n\t"
-            "CMP_w    $tmp, $oldval\n\t"
-            "B.ne     done\n\t"
-            "STXR_w   $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop\n\t"
-            "done:\n\t"
-            "CSET_w   $res, eq" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    Label loop, done;
-    __ bind(loop);
-    __ ldxr_w($tmp$$Register, base);
-    __ cmp_w($tmp$$Register, $oldval$$Register);
-    __ b(done, ne);
-    __ stxr_w($tmp$$Register, $newval$$Register,  base);
-    __ cbnz_w($tmp$$Register, loop);
-    __ bind(done);
-    __ cset_w($res$$Register, eq);
-  %}
-  ins_pipe( long_memory_op );
-%}
-
-instruct compareAndSwapP_bool(memoryex mem, iRegP oldval, iRegP newval, iRegI res, iRegI tmp, flagsReg ccr) %{
-  match(Set res (CompareAndSwapP mem (Binary oldval newval)));
-  effect( KILL ccr, TEMP tmp);
-  size(24);
-  format %{ "loop:\n\t"
-            "LDXR     $tmp, $mem\t! If $oldval==[$mem] Then store $newval into [$mem]\n\t"
-            "CMP      $tmp, $oldval\n\t"
-            "B.ne     done\n\t"
-            "STXR     $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop\n\t"
-            "done:\n\t"
-            "CSET_w   $res, eq" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    Label loop, done;
-    __ bind(loop);
-    __ ldxr($tmp$$Register, base);
-    __ cmp($tmp$$Register, $oldval$$Register);
-    __ b(done, ne);
-    __ stxr($tmp$$Register, $newval$$Register,  base);
-    __ cbnz_w($tmp$$Register, loop);
-    __ bind(done);
-    __ cset_w($res$$Register, eq);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else // !AARCH64
 instruct compareAndSwapL_bool(memoryex mem, iRegL oldval, iRegLd newval, iRegI res, iRegLd tmp, flagsReg ccr ) %{
   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
   effect( KILL ccr, TEMP tmp);
@@ -7488,32 +5580,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif // !AARCH64
-
-#ifdef AARCH64
-instruct xaddI_aimmI_no_res(memoryex mem, aimmI add, Universe dummy, iRegI tmp1, iRegI tmp2) %{
-  predicate(n->as_LoadStore()->result_not_used());
-  match(Set dummy (GetAndAddI mem add));
-  effect(TEMP tmp1, TEMP tmp2);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR_w   $tmp1, $mem\n\t"
-            "ADD_w    $tmp1, $tmp1, $add\n\t"
-            "STXR_w   $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($tmp1$$Register, base);
-    __ add_w($tmp1$$Register, $tmp1$$Register, $add$$constant);
-    __ stxr_w($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddI_aimmI_no_res(memoryex mem, aimmI add, Universe dummy, iRegI tmp1, iRegI tmp2, flagsReg ccr) %{
   predicate(n->as_LoadStore()->result_not_used());
   match(Set dummy (GetAndAddI mem add));
@@ -7537,32 +5604,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddI_reg_no_res(memoryex mem, iRegI add, Universe dummy, iRegI tmp1, iRegI tmp2) %{
-  predicate(n->as_LoadStore()->result_not_used());
-  match(Set dummy (GetAndAddI mem add));
-  effect(TEMP tmp1, TEMP tmp2);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR_w   $tmp1, $mem\n\t"
-            "ADD_w    $tmp1, $tmp1, $add\n\t"
-            "STXR_w   $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($tmp1$$Register, base);
-    __ add_w($tmp1$$Register, $tmp1$$Register, $add$$Register);
-    __ stxr_w($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddI_reg_no_res(memoryex mem, iRegI add, Universe dummy, iRegI tmp1, iRegI tmp2, flagsReg ccr) %{
   predicate(n->as_LoadStore()->result_not_used());
   match(Set dummy (GetAndAddI mem add));
@@ -7586,31 +5628,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddI_aimmI(memoryex mem, aimmI add, iRegI res, iRegI tmp1, iRegI tmp2) %{
-  match(Set res (GetAndAddI mem add));
-  effect(TEMP tmp1, TEMP tmp2, TEMP res);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR_w   $res, $mem\n\t"
-            "ADD_w    $tmp1, $res, $add\n\t"
-            "STXR_w   $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($res$$Register, base);
-    __ add_w($tmp1$$Register, $res$$Register, $add$$constant);
-    __ stxr_w($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddI_aimmI(memoryex mem, aimmI add, iRegI res, iRegI tmp1, iRegI tmp2, flagsReg ccr) %{
   match(Set res (GetAndAddI mem add));
   effect(KILL ccr, TEMP tmp1, TEMP tmp2, TEMP res);
@@ -7633,31 +5651,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddI_reg(memoryex mem, iRegI add, iRegI res, iRegI tmp1, iRegI tmp2) %{
-  match(Set res (GetAndAddI mem add));
-  effect(TEMP tmp1, TEMP tmp2, TEMP res);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR_w   $res, $mem\n\t"
-            "ADD_w    $tmp1, $res, $add\n\t"
-            "STXR_w   $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($res$$Register, base);
-    __ add_w($tmp1$$Register, $res$$Register, $add$$Register);
-    __ stxr_w($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddI_reg(memoryex mem, iRegI add, iRegI res, iRegI tmp1, iRegI tmp2, flagsReg ccr) %{
   match(Set res (GetAndAddI mem add));
   effect(KILL ccr, TEMP tmp1, TEMP tmp2, TEMP res);
@@ -7680,32 +5674,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddL_reg_no_res(memoryex mem, iRegL add, Universe dummy, iRegL tmp1, iRegI tmp2) %{
-  predicate(n->as_LoadStore()->result_not_used());
-  match(Set dummy (GetAndAddL mem add));
-  effect(TEMP tmp1, TEMP tmp2);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR     $tmp1, $mem\n\t"
-            "ADD      $tmp1, $tmp1, $add\n\t"
-            "STXR     $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr($tmp1$$Register, base);
-    __ add($tmp1$$Register, $tmp1$$Register, $add$$Register);
-    __ stxr($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddL_reg_no_res(memoryex mem, iRegL add, Universe dummy, iRegLd tmp1, iRegI tmp2, flagsReg ccr) %{
   predicate(n->as_LoadStore()->result_not_used());
   match(Set dummy (GetAndAddL mem add));
@@ -7731,32 +5700,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddL_imm_no_res(memoryex mem, aimmL add, Universe dummy, iRegL tmp1, iRegI tmp2) %{
-  predicate(n->as_LoadStore()->result_not_used());
-  match(Set dummy (GetAndAddL mem add));
-  effect(TEMP tmp1, TEMP tmp2);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR     $tmp1, $mem\n\t"
-            "ADD      $tmp1, $tmp1, $add\n\t"
-            "STXR     $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr($tmp1$$Register, base);
-    __ add($tmp1$$Register, $tmp1$$Register, $add$$constant);
-    __ stxr($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct xaddL_immRot_no_res(memoryex mem, immLlowRot add, Universe dummy, iRegLd tmp1, iRegI tmp2, flagsReg ccr) %{
@@ -7784,31 +5728,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddL_reg(memoryex mem, iRegL add, iRegL res, iRegL tmp1, iRegI tmp2) %{
-  match(Set res (GetAndAddL mem add));
-  effect(TEMP tmp1, TEMP tmp2, TEMP res);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR     $res, $mem\n\t"
-            "ADD      $tmp1, $res, $add\n\t"
-            "STXR     $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr($res$$Register, base);
-    __ add($tmp1$$Register, $res$$Register, $add$$Register);
-    __ stxr($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddL_reg(memoryex mem, iRegL add, iRegLd res, iRegLd tmp1, iRegI tmp2, flagsReg ccr) %{
   match(Set res (GetAndAddL mem add));
   effect( KILL ccr, TEMP tmp1, TEMP tmp2, TEMP res);
@@ -7833,31 +5753,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddL_imm(memoryex mem, aimmL add, iRegL res, iRegL tmp1, iRegI tmp2) %{
-  match(Set res (GetAndAddL mem add));
-  effect(TEMP tmp1, TEMP tmp2, TEMP res);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR     $res, $mem\n\t"
-            "ADD      $tmp1, $res, $add\n\t"
-            "STXR     $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr($res$$Register, base);
-    __ add($tmp1$$Register, $res$$Register, $add$$constant);
-    __ stxr($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct xaddL_immRot(memoryex mem, immLlowRot add, iRegLd res, iRegLd tmp1, iRegI tmp2, flagsReg ccr) %{
@@ -7884,52 +5780,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xchgI(memoryex mem, iRegI newval, iRegI res, iRegI tmp) %{
-  match(Set res (GetAndSetI mem newval));
-  effect(TEMP tmp, TEMP res);
-  size(12);
-  format %{ "loop:\n\t"
-            "LDXR_w   $res, $mem\n\t"
-            "STXR_w   $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($res$$Register, base);
-    __ stxr_w($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-
-#ifdef XXX
-// Disabled until 8051805 is fixed.
-instruct xchgN(memoryex mem, iRegN newval, iRegN res, iRegN tmp) %{
-  match(Set res (GetAndSetN mem newval));
-  effect(TEMP tmp, TEMP res);
-  size(12);
-  format %{ "loop:\n\t"
-            "LDXR_w   $res, $mem\n\t"
-            "STXR_w   $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($res$$Register, base);
-    __ stxr_w($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#endif
-#else
+
 instruct xchgI(memoryex mem, iRegI newval, iRegI res, iRegI tmp, flagsReg ccr) %{
   match(Set res (GetAndSetI mem newval));
   effect(KILL ccr, TEMP tmp, TEMP res);
@@ -7950,29 +5801,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xchgL(memoryex mem, iRegL newval, iRegL res, iRegI tmp) %{
-  match(Set res (GetAndSetL mem newval));
-  effect(TEMP tmp, TEMP res);
-  size(12);
-  format %{ "loop:\n\t"
-            "LDXR     $res, $mem\n\t"
-            "STXR     $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr($res$$Register, base);
-    __ stxr($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xchgL(memoryex mem, iRegLd newval, iRegLd res, iRegI tmp, flagsReg ccr) %{
   match(Set res (GetAndSetL mem newval));
   effect( KILL ccr, TEMP tmp, TEMP res);
@@ -7993,29 +5822,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif // !AARCH64
-
-#ifdef AARCH64
-instruct xchgP(memoryex mem, iRegP newval, iRegP res, iRegI tmp) %{
-  match(Set res (GetAndSetP mem newval));
-  effect(TEMP tmp, TEMP res);
-  size(12);
-  format %{ "loop:\n\t"
-            "LDREX    $res, $mem\n\t"
-            "STREX    $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldrex($res$$Register, base);
-    __ strex($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xchgP(memoryex mem, iRegP newval, iRegP res, iRegI tmp, flagsReg ccr) %{
   match(Set res (GetAndSetP mem newval));
   effect(KILL ccr, TEMP tmp, TEMP res);
@@ -8036,7 +5843,6 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif // !AARCH64
 
 //---------------------
 // Subtraction Instructions
@@ -8052,7 +5858,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct subshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (SubI src1 (LShiftI src2 src3)));
 
@@ -8063,7 +5868,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct subshlI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (SubI src1 (LShiftI src2 src3)));
@@ -8076,7 +5880,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct subsarI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (SubI src1 (RShiftI src2 src3)));
 
@@ -8087,7 +5890,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct subsarI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (SubI src1 (RShiftI src2 src3)));
@@ -8100,7 +5902,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct subshrI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (SubI src1 (URShiftI src2 src3)));
 
@@ -8111,7 +5912,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct subshrI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (SubI src1 (URShiftI src2 src3)));
@@ -8124,7 +5924,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct rsbshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (SubI (LShiftI src1 src2) src3));
 
@@ -8190,7 +5989,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 // Immediate Subtraction
 instruct subI_reg_aimmI(iRegI dst, iRegI src1, aimmI src2) %{
@@ -8215,7 +6013,6 @@
   ins_pipe(ialu_reg_imm);
 %}
 
-#ifndef AARCH64
 instruct subI_immRot_reg(iRegI dst, immIRot src1, iRegI src2) %{
   match(Set dst (SubI src1 src2));
 
@@ -8226,21 +6023,8 @@
   %}
   ins_pipe(ialu_zero_reg);
 %}
-#endif
 
 // Register Subtraction
-#ifdef AARCH64
-instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (SubL src1 src2));
-
-  size(4);
-  format %{ "SUB    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ sub($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-#else
 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2, flagsReg icc ) %{
   match(Set dst (SubL src1 src2));
   effect (KILL icc);
@@ -8254,36 +6038,9 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
-
-#ifdef AARCH64
-// Immediate Subtraction
-instruct subL_reg_aimm(iRegL dst, iRegL src1, aimmL src2) %{
-  match(Set dst (SubL src1 src2));
-
-  size(4);
-  format %{ "SUB    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ sub($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-
-instruct subL_reg_immLneg(iRegL dst, iRegL src1, aimmLneg src2) %{
-  match(Set dst (AddL src1 src2));
-
-  size(4);
-  format %{ "SUB    $dst,$src1,-($src2)\t! long" %}
-  ins_encode %{
-    __ sub($dst$$Register, $src1$$Register, -$src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
+
 // TODO
-#endif
-
-#ifndef AARCH64
+
 // Immediate Subtraction
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
@@ -8315,7 +6072,6 @@
   %}
   ins_pipe(ialu_zero_reg);
 %}
-#endif // !AARCH64
 
 // Multiplication Instructions
 // Integer Multiplication
@@ -8331,17 +6087,6 @@
   ins_pipe(imul_reg_reg);
 %}
 
-#ifdef AARCH64
-instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (MulL src1 src2));
-  size(4);
-  format %{ "MUL  $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ mul($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(imul_reg_reg);
-%}
-#else
 instruct mulL_lo1_hi2(iRegL dst, iRegL src1, iRegL src2) %{
   effect(DEF dst, USE src1, USE src2);
   size(4);
@@ -8383,22 +6128,9 @@
     mulL_lo1_lo2(dst, src1, src2);
   %}
 %}
-#endif // !AARCH64
 
 // Integer Division
 // Register Division
-#ifdef AARCH64
-instruct divI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
-  match(Set dst (DivI src1 src2));
-
-  size(4);
-  format %{ "SDIV    $dst,$src1,$src2\t! 32-bit" %}
-  ins_encode %{
-    __ sdiv_w($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-%}
-#else
 instruct divI_reg_reg(R1RegI dst, R0RegI src1, R2RegI src2, LRRegP lr, flagsReg ccr) %{
   match(Set dst (DivI src1 src2));
   effect( KILL ccr, KILL src1, KILL src2, KILL lr);
@@ -8410,21 +6142,8 @@
   %}
   ins_pipe(sdiv_reg_reg);
 %}
-#endif
 
 // Register Long Division
-#ifdef AARCH64
-instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (DivL src1 src2));
-
-  size(4);
-  format %{ "SDIV    $dst,$src1,$src2" %}
-  ins_encode %{
-    __ sdiv($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-%}
-#else
 instruct divL_reg_reg(R0R1RegL dst, R2R3RegL src1, R0R1RegL src2) %{
   match(Set dst (DivL src1 src2));
   effect(CALL);
@@ -8436,38 +6155,9 @@
   %}
   ins_pipe(divL_reg_reg);
 %}
-#endif
 
 // Integer Remainder
 // Register Remainder
-#ifdef AARCH64
-#ifdef TODO
-instruct msubI_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
-  match(Set dst (SubI src1 (MulI src2 src3)));
-
-  size(4);
-  format %{ "MSUB    $dst,$src2,$src3,$src1\t! 32-bit\n\t" %}
-  ins_encode %{
-    __ msub_w($dst$$Register, $src2$$Register, $src3$$Register, $src1$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-%}
-#endif
-
-instruct modI_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp) %{
-  match(Set dst (ModI src1 src2));
-  effect(TEMP temp);
-
-  size(8);
-  format %{ "SDIV    $temp,$src1,$src2\t! 32-bit\n\t"
-            "MSUB    $dst,$src2,$temp,$src1\t! 32-bit\n\t" %}
-  ins_encode %{
-    __ sdiv_w($temp$$Register, $src1$$Register, $src2$$Register);
-    __ msub_w($dst$$Register, $src2$$Register, $temp$$Register, $src1$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-%}
-#else
 instruct modI_reg_reg(R0RegI dst, R0RegI src1, R2RegI src2, R1RegI temp, LRRegP lr, flagsReg ccr ) %{
   match(Set dst (ModI src1 src2));
   effect( KILL ccr, KILL temp, KILL src2, KILL lr);
@@ -8478,24 +6168,8 @@
   %}
   ins_pipe(sdiv_reg_reg);
 %}
-#endif
 
 // Register Long Remainder
-#ifdef AARCH64
-instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2, iRegL temp) %{
-  match(Set dst (ModL src1 src2));
-  effect(TEMP temp);
-
-  size(8);
-  format %{ "SDIV    $temp,$src1,$src2\n\t"
-            "MSUB    $dst,$src2,$temp,$src1" %}
-  ins_encode %{
-    __ sdiv($temp$$Register, $src1$$Register, $src2$$Register);
-    __ msub($dst$$Register, $src2$$Register, $temp$$Register, $src1$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-%}
-#else
 instruct modL_reg_reg(R0R1RegL dst, R2R3RegL src1, R0R1RegL src2) %{
   match(Set dst (ModL src1 src2));
   effect(CALL);
@@ -8507,7 +6181,6 @@
   %}
   ins_pipe(divL_reg_reg);
 %}
-#endif
 
 // Integer Shift Instructions
 
@@ -8516,17 +6189,10 @@
   match(Set dst (LShiftI src1 src2));
 
   size(4);
-#ifdef AARCH64
-  format %{ "LSLV   $dst,$src1,$src2\t! int" %}
-  ins_encode %{
-    __ lslv_w($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   format %{ "LSL  $dst,$src1,$src2 \n\t" %}
   ins_encode %{
     __ mov($dst$$Register, AsmOperand($src1$$Register, lsl, $src2$$Register));
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
@@ -8535,21 +6201,13 @@
   match(Set dst (LShiftI src1 src2));
 
   size(4);
-#ifdef AARCH64
-  format %{ "LSL_w  $dst,$src1,$src2\t! int" %}
-  ins_encode %{
-    __ _lsl($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-#else
   format %{ "LSL    $dst,$src1,$src2\t! int" %}
   ins_encode %{
     __ logical_shift_left($dst$$Register, $src1$$Register, $src2$$constant);
   %}
-#endif
   ins_pipe(ialu_reg_imm);
 %}
 
-#ifndef AARCH64
 instruct shlL_reg_reg_merge_hi(iRegL dst, iRegL src1, iRegI src2) %{
   effect(USE_DEF dst, USE src1, USE src2);
   size(4);
@@ -8587,40 +6245,18 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif // !AARCH64
 
 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
   match(Set dst (LShiftL src1 src2));
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LSLV  $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ lslv($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg);
-#else
   expand %{
     flagsReg ccr;
     shlL_reg_reg_overlap(dst, src1, src2, ccr);
     shlL_reg_reg_merge_hi(dst, src1, src2);
     shlL_reg_reg_merge_lo(dst, src1, src2);
   %}
-#endif
-%}
-
-#ifdef AARCH64
-instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
-  match(Set dst (LShiftL src1 src2));
-
-  size(4);
-  format %{ "LSL    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ logical_shift_left($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
+%}
+
 // Register Shift Left Immediate
 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6Big src2) %{
   match(Set dst (LShiftL src1 src2));
@@ -8655,23 +6291,15 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif // !AARCH64
 
 // Register Arithmetic Shift Right
 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
   match(Set dst (RShiftI src1 src2));
   size(4);
-#ifdef AARCH64
-  format %{ "ASRV   $dst,$src1,$src2\t! int" %}
-  ins_encode %{
-    __ asrv_w($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   format %{ "ASR    $dst,$src1,$src2\t! int" %}
   ins_encode %{
     __ mov($dst$$Register, AsmOperand($src1$$Register, asr, $src2$$Register));
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
@@ -8680,21 +6308,13 @@
   match(Set dst (RShiftI src1 src2));
 
   size(4);
-#ifdef AARCH64
-  format %{ "ASR_w  $dst,$src1,$src2" %}
-  ins_encode %{
-    __ _asr_w($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-#else
   format %{ "ASR    $dst,$src1,$src2" %}
   ins_encode %{
     __ mov($dst$$Register, AsmOperand($src1$$Register, asr, $src2$$constant));
   %}
-#endif
   ins_pipe(ialu_reg_imm);
 %}
 
-#ifndef AARCH64
 // Register Shift Right Arithmetic Long
 instruct sarL_reg_reg_merge_lo(iRegL dst, iRegL src1, iRegI src2) %{
   effect(USE_DEF dst, USE src1, USE src2);
@@ -8733,41 +6353,19 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif // !AARCH64
 
 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
   match(Set dst (RShiftL src1 src2));
 
-#ifdef AARCH64
-  size(4);
-  format %{ "ASRV  $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ asrv($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg);
-#else
   expand %{
     flagsReg ccr;
     sarL_reg_reg_overlap(dst, src1, src2, ccr);
     sarL_reg_reg_merge_lo(dst, src1, src2);
     sarL_reg_reg_merge_hi(dst, src1, src2);
   %}
-#endif
 %}
 
 // Register Shift Left Immediate
-#ifdef AARCH64
-instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
-  match(Set dst (RShiftL src1 src2));
-
-  size(4);
-  format %{ "ASR    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ _asr($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6Big src2) %{
   match(Set dst (RShiftL src1 src2));
 
@@ -8801,23 +6399,15 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 // Register Shift Right
 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
   match(Set dst (URShiftI src1 src2));
   size(4);
-#ifdef AARCH64
-  format %{ "LSRV   $dst,$src1,$src2\t! int" %}
-  ins_encode %{
-    __ lsrv_w($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   format %{ "LSR    $dst,$src1,$src2\t! int" %}
   ins_encode %{
     __ mov($dst$$Register, AsmOperand($src1$$Register, lsr, $src2$$Register));
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
@@ -8826,21 +6416,13 @@
   match(Set dst (URShiftI src1 src2));
 
   size(4);
-#ifdef AARCH64
-  format %{ "LSR_w  $dst,$src1,$src2" %}
-  ins_encode %{
-    __ _lsr_w($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-#else
   format %{ "LSR    $dst,$src1,$src2" %}
   ins_encode %{
     __ mov($dst$$Register, AsmOperand($src1$$Register, lsr, $src2$$constant));
   %}
-#endif
   ins_pipe(ialu_reg_imm);
 %}
 
-#ifndef AARCH64
 // Register Shift Right
 instruct shrL_reg_reg_merge_lo(iRegL dst, iRegL src1, iRegI src2) %{
   effect(USE_DEF dst, USE src1, USE src2);
@@ -8879,41 +6461,19 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif // !AARCH64
 
 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
   match(Set dst (URShiftL src1 src2));
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LSRV  $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ lsrv($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg);
-#else
   expand %{
     flagsReg ccr;
     shrL_reg_reg_overlap(dst, src1, src2, ccr);
     shrL_reg_reg_merge_lo(dst, src1, src2);
     shrL_reg_reg_merge_hi(dst, src1, src2);
   %}
-#endif
 %}
 
 // Register Shift Right Immediate
-#ifdef AARCH64
-instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
-  match(Set dst (URShiftL src1 src2));
-
-  size(4);
-  format %{ "LSR    $dst,$src1,$src2" %}
-  ins_encode %{
-    __ _lsr($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6Big src2) %{
   match(Set dst (URShiftL src1 src2));
 
@@ -8948,7 +6508,6 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif // !AARCH64
 
 
 instruct shrP_reg_imm5(iRegX dst, iRegP src1, immU5 src2) %{
@@ -9146,7 +6705,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct andshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AndI src1 (LShiftI src2 src3)));
 
@@ -9157,7 +6715,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct andshlI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (AndI src1 (LShiftI src2 src3)));
@@ -9170,7 +6727,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct andsarI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AndI src1 (RShiftI src2 src3)));
 
@@ -9181,7 +6737,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct andsarI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (AndI src1 (RShiftI src2 src3)));
@@ -9194,7 +6749,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct andshrI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AndI src1 (URShiftI src2 src3)));
 
@@ -9205,7 +6759,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct andshrI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (AndI src1 (URShiftI src2 src3)));
@@ -9230,7 +6783,6 @@
   ins_pipe(ialu_reg_imm);
 %}
 
-#ifndef AARCH64
 instruct andI_reg_limmn(iRegI dst, iRegI src1, limmIn src2) %{
   match(Set dst (AndI src1 src2));
 
@@ -9241,43 +6793,21 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 // Register And Long
 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
   match(Set dst (AndL src1 src2));
 
   ins_cost(DEFAULT_COST);
-#ifdef AARCH64
-  size(4);
-  format %{ "AND    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ andr($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   size(8);
   format %{ "AND    $dst,$src1,$src2\t! long" %}
   ins_encode %{
     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
     __ andr($dst$$Register->successor(), $src1$$Register->successor(), $src2$$Register->successor());
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifdef AARCH64
-// Immediate And
-instruct andL_reg_limm(iRegL dst, iRegL src1, limmL src2) %{
-  match(Set dst (AndL src1 src2));
-
-  size(4);
-  format %{ "AND    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ andr($dst$$Register, $src1$$Register, (uintx)$src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct andL_reg_immRot(iRegL dst, iRegL src1, immLlowRot con) %{
@@ -9291,7 +6821,6 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 // Or Instructions
 // Register Or
@@ -9306,7 +6835,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct orshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (OrI src1 (LShiftI src2 src3)));
 
@@ -9317,7 +6845,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct orshlI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (OrI src1 (LShiftI src2 src3)));
@@ -9330,7 +6857,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct orsarI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (OrI src1 (RShiftI src2 src3)));
 
@@ -9341,7 +6867,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct orsarI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (OrI src1 (RShiftI src2 src3)));
@@ -9354,7 +6879,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct orshrI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (OrI src1 (URShiftI src2 src3)));
 
@@ -9365,7 +6889,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct orshrI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (OrI src1 (URShiftI src2 src3)));
@@ -9396,13 +6919,6 @@
   match(Set dst (OrL src1 src2));
 
   ins_cost(DEFAULT_COST);
-#ifdef AARCH64
-  size(4);
-  format %{ "OR     $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ orr($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   size(8);
   format %{ "OR     $dst.lo,$src1.lo,$src2.lo\t! long\n\t"
             "OR     $dst.hi,$src1.hi,$src2.hi" %}
@@ -9410,22 +6926,9 @@
     __ orr($dst$$Register, $src1$$Register, $src2$$Register);
     __ orr($dst$$Register->successor(), $src1$$Register->successor(), $src2$$Register->successor());
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifdef AARCH64
-instruct orL_reg_limm(iRegL dst, iRegL src1, limmL src2) %{
-  match(Set dst (OrL src1 src2));
-
-  size(4);
-  format %{ "ORR    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ orr($dst$$Register, $src1$$Register, (uintx)$src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct orL_reg_immRot(iRegL dst, iRegL src1, immLlowRot con) %{
@@ -9440,7 +6943,6 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 #ifdef TODO
 // Use SPRegP to match Rthread (TLS register) without spilling.
@@ -9470,7 +6972,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct xorshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (XorI src1 (LShiftI src2 src3)));
 
@@ -9481,7 +6982,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct xorshlI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (XorI src1 (LShiftI src2 src3)));
@@ -9494,7 +6994,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct xorsarI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (XorI src1 (RShiftI src2 src3)));
 
@@ -9505,7 +7004,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct xorsarI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (XorI src1 (RShiftI src2 src3)));
@@ -9518,7 +7016,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct xorshrI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (XorI src1 (URShiftI src2 src3)));
 
@@ -9529,7 +7026,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct xorshrI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (XorI src1 (URShiftI src2 src3)));
@@ -9558,13 +7054,6 @@
 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
   match(Set dst (XorL src1 src2));
   ins_cost(DEFAULT_COST);
-#ifdef AARCH64
-  size(4);
-  format %{ "XOR     $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ eor($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   size(8);
   format %{ "XOR     $dst.hi,$src1.hi,$src2.hi\t! long\n\t"
             "XOR     $dst.lo,$src1.lo,$src2.lo\t! long" %}
@@ -9572,22 +7061,9 @@
     __ eor($dst$$Register, $src1$$Register, $src2$$Register);
     __ eor($dst$$Register->successor(), $src1$$Register->successor(), $src2$$Register->successor());
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifdef AARCH64
-instruct xorL_reg_limmL(iRegL dst, iRegL src1, limmL con) %{
-  match(Set dst (XorL src1 con));
-  ins_cost(DEFAULT_COST);
-  size(4);
-  format %{ "EOR     $dst,$src1,$con\t! long" %}
-  ins_encode %{
-    __ eor($dst$$Register, $src1$$Register, (uintx)$con$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct xorL_reg_immRot(iRegL dst, iRegL src1, immLlowRot con) %{
@@ -9602,22 +7078,11 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif // AARCH64
 
 //----------Convert to Boolean-------------------------------------------------
 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
   match(Set dst (Conv2B src));
   effect(KILL ccr);
-#ifdef AARCH64
-  size(8);
-  ins_cost(DEFAULT_COST*2);
-  format %{ "cmp_32 $src,ZR\n\t"
-            "cset_w $dst, ne" %}
-  ins_encode %{
-    __ cmp_32($src$$Register, ZR);
-    __ cset_w($dst$$Register, ne);
-  %}
-#else
   size(12);
   ins_cost(DEFAULT_COST*2);
   format %{ "TST    $src,$src \n\t"
@@ -9628,23 +7093,12 @@
     __ mov($dst$$Register, 0);
     __ mov($dst$$Register, 1, ne);
   %}
-#endif
   ins_pipe(ialu_reg_ialu);
 %}
 
 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
   match(Set dst (Conv2B src));
   effect(KILL ccr);
-#ifdef AARCH64
-  size(8);
-  ins_cost(DEFAULT_COST*2);
-  format %{ "CMP    $src,ZR\n\t"
-            "cset   $dst, ne" %}
-  ins_encode %{
-    __ cmp($src$$Register, ZR);
-    __ cset($dst$$Register, ne);
-  %}
-#else
   size(12);
   ins_cost(DEFAULT_COST*2);
   format %{ "TST    $src,$src \n\t"
@@ -9655,23 +7109,12 @@
     __ mov($dst$$Register, 0);
     __ mov($dst$$Register, 1, ne);
   %}
-#endif
   ins_pipe(ialu_reg_ialu);
 %}
 
 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
   match(Set dst (CmpLTMask p q));
   effect( KILL ccr );
-#ifdef AARCH64
-  size(8);
-  ins_cost(DEFAULT_COST*2);
-  format %{ "CMP_w   $p,$q\n\t"
-            "CSETM_w $dst, lt" %}
-  ins_encode %{
-    __ cmp_w($p$$Register, $q$$Register);
-    __ csetm_w($dst$$Register, lt);
-  %}
-#else
   ins_cost(DEFAULT_COST*3);
   format %{ "CMP    $p,$q\n\t"
             "MOV    $dst, #0\n\t"
@@ -9681,23 +7124,12 @@
     __ mov($dst$$Register, 0);
     __ mvn($dst$$Register, 0, lt);
   %}
-#endif
   ins_pipe(ialu_reg_reg_ialu);
 %}
 
 instruct cmpLTMask_reg_imm( iRegI dst, iRegI p, aimmI q, flagsReg ccr ) %{
   match(Set dst (CmpLTMask p q));
   effect( KILL ccr );
-#ifdef AARCH64
-  size(8);
-  ins_cost(DEFAULT_COST*2);
-  format %{ "CMP_w   $p,$q\n\t"
-            "CSETM_w $dst, lt" %}
-  ins_encode %{
-    __ cmp_w($p$$Register, $q$$constant);
-    __ csetm_w($dst$$Register, lt);
-  %}
-#else
   ins_cost(DEFAULT_COST*3);
   format %{ "CMP    $p,$q\n\t"
             "MOV    $dst, #0\n\t"
@@ -9707,27 +7139,9 @@
     __ mov($dst$$Register, 0);
     __ mvn($dst$$Register, 0, lt);
   %}
-#endif
   ins_pipe(ialu_reg_reg_ialu);
 %}
 
-#ifdef AARCH64
-instruct cadd_cmpLTMask3( iRegI dst, iRegI p, iRegI q, iRegI y, iRegI x, flagsReg ccr ) %{
-  match(Set dst (AddI (AndI (CmpLTMask p q) y) x));
-  effect( TEMP dst, KILL ccr );
-  size(12);
-  ins_cost(DEFAULT_COST*3);
-  format %{ "CMP_w  $p,$q\n\t"
-            "ADD_w  $dst,$y,$x\n\t"
-            "CSEL_w $dst,$dst,$x,lt" %}
-  ins_encode %{
-    __ cmp_w($p$$Register, $q$$Register);
-    __ add_w($dst$$Register, $y$$Register, $x$$Register);
-    __ csel_w($dst$$Register, $dst$$Register, $x$$Register, lt);
-  %}
-  ins_pipe( cadd_cmpltmask );
-%}
-#else
 instruct cadd_cmpLTMask3( iRegI p, iRegI q, iRegI y, iRegI z, flagsReg ccr ) %{
   match(Set z (AddI (AndI (CmpLTMask p q) y) z));
   effect( KILL ccr );
@@ -9740,25 +7154,7 @@
   %}
   ins_pipe( cadd_cmpltmask );
 %}
-#endif
-
-#ifdef AARCH64
-instruct cadd_cmpLTMask4( iRegI dst, iRegI p, aimmI q, iRegI y, iRegI x, flagsReg ccr ) %{
-  match(Set dst (AddI (AndI (CmpLTMask p q) y) x));
-  effect( TEMP dst, KILL ccr );
-  size(12);
-  ins_cost(DEFAULT_COST*3);
-  format %{ "CMP_w  $p,$q\n\t"
-            "ADD_w  $dst,$y,$x\n\t"
-            "CSEL_w $dst,$dst,$x,lt" %}
-  ins_encode %{
-    __ cmp_w($p$$Register, $q$$constant);
-    __ add_w($dst$$Register, $y$$Register, $x$$Register);
-    __ csel_w($dst$$Register, $dst$$Register, $x$$Register, lt);
-  %}
-  ins_pipe( cadd_cmpltmask );
-%}
-#else
+
 // FIXME: remove unused "dst"
 instruct cadd_cmpLTMask4( iRegI dst, iRegI p, aimmI q, iRegI y, iRegI z, flagsReg ccr ) %{
   match(Set z (AddI (AndI (CmpLTMask p q) y) z));
@@ -9772,25 +7168,7 @@
   %}
   ins_pipe( cadd_cmpltmask );
 %}
-#endif // !AARCH64
-
-#ifdef AARCH64
-instruct cadd_cmpLTMask( iRegI dst, iRegI p, iRegI q, iRegI y, flagsReg ccr ) %{
-  match(Set dst (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
-  effect( TEMP dst, KILL ccr );
-  size(12);
-  ins_cost(DEFAULT_COST*3);
-  format %{ "SUBS_w $p,$p,$q\n\t"
-            "ADD_w  $dst,$y,$p\n\t"
-            "CSEL_w $dst,$dst,$p,lt" %}
-  ins_encode %{
-    __ subs_w($p$$Register, $p$$Register, $q$$Register);
-    __ add_w($dst$$Register, $y$$Register, $p$$Register);
-    __ csel_w($dst$$Register, $dst$$Register, $p$$Register, lt);
-  %}
-  ins_pipe( cadd_cmpltmask ); // FIXME
-%}
-#else
+
 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, flagsReg ccr ) %{
   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
   effect( KILL ccr );
@@ -9803,7 +7181,6 @@
   %}
   ins_pipe( cadd_cmpltmask );
 %}
-#endif
 
 //----------Arithmetic Conversion Instructions---------------------------------
 // The conversions operations are all Alpha sorted.  Please keep it that way!
@@ -9821,27 +7198,6 @@
 // Convert a double to an int in a float register.
 // If the double is a NAN, stuff a zero in instead.
 
-#ifdef AARCH64
-instruct convD2I_reg_reg(iRegI dst, regD src) %{
-  match(Set dst (ConvD2I src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  format %{ "FCVTZS_wd $dst, $src" %}
-  ins_encode %{
-    __ fcvtzs_wd($dst$$Register, $src$$FloatRegister);
-  %}
-  ins_pipe(fcvtD2I);
-%}
-
-instruct convD2L_reg_reg(iRegL dst, regD src) %{
-  match(Set dst (ConvD2L src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  format %{ "FCVTZS_xd $dst, $src" %}
-  ins_encode %{
-    __ fcvtzs_xd($dst$$Register, $src$$FloatRegister);
-  %}
-  ins_pipe(fcvtD2L);
-%}
-#else
 instruct convD2I_reg_reg(iRegI dst, regD src, regF tmp) %{
   match(Set dst (ConvD2I src));
   effect( TEMP tmp );
@@ -9854,12 +7210,10 @@
   %}
   ins_pipe(fcvtD2I);
 %}
-#endif
 
 // Convert a double to a long in a double register.
 // If the double is a NAN, stuff a zero in instead.
 
-#ifndef AARCH64
 // Double to Long conversion
 instruct convD2L_reg(R0R1RegL dst, regD src) %{
   match(Set dst (ConvD2L src));
@@ -9879,7 +7233,6 @@
   %}
   ins_pipe(fcvtD2L);
 %}
-#endif
 
 instruct convF2D_reg(regD dst, regF src) %{
   match(Set dst (ConvF2D src));
@@ -9891,29 +7244,6 @@
   ins_pipe(fcvtF2D);
 %}
 
-#ifdef AARCH64
-instruct convF2I_reg_reg(iRegI dst, regF src) %{
-  match(Set dst (ConvF2I src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  size(4);
-  format %{ "FCVTZS_ws $dst, $src" %}
-  ins_encode %{
-    __ fcvtzs_ws($dst$$Register, $src$$FloatRegister);
-  %}
-  ins_pipe(fcvtF2I);
-%}
-
-instruct convF2L_reg_reg(iRegL dst, regF src) %{
-  match(Set dst (ConvF2L src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  size(4);
-  format %{ "FCVTZS_xs $dst, $src" %}
-  ins_encode %{
-    __ fcvtzs_xs($dst$$Register, $src$$FloatRegister);
-  %}
-  ins_pipe(fcvtF2L);
-%}
-#else
 instruct convF2I_reg_reg(iRegI dst, regF src, regF tmp) %{
   match(Set dst (ConvF2I src));
   effect( TEMP tmp );
@@ -9947,20 +7277,7 @@
   %}
   ins_pipe(fcvtF2L);
 %}
-#endif
-
-#ifdef AARCH64
-instruct convI2D_reg_reg(iRegI src, regD dst) %{
-  match(Set dst (ConvI2D src));
-  ins_cost(DEFAULT_COST + MEMORY_REF_COST); // FIXME
-  size(4);
-  format %{ "SCVTF_dw $dst,$src" %}
-  ins_encode %{
-      __ scvtf_dw($dst$$FloatRegister, $src$$Register);
-  %}
-  ins_pipe(fcvtI2D);
-%}
-#else
+
 instruct convI2D_reg_reg(iRegI src, regD_low dst) %{
   match(Set dst (ConvI2D src));
   ins_cost(DEFAULT_COST + MEMORY_REF_COST); // FIXME
@@ -9973,18 +7290,10 @@
   %}
   ins_pipe(fcvtI2D);
 %}
-#endif
 
 instruct convI2F_reg_reg( regF dst, iRegI src ) %{
   match(Set dst (ConvI2F src));
   ins_cost(DEFAULT_COST + MEMORY_REF_COST); // FIXME
-#ifdef AARCH64
-  size(4);
-  format %{ "SCVTF_sw $dst,$src" %}
-  ins_encode %{
-      __ scvtf_sw($dst$$FloatRegister, $src$$Register);
-  %}
-#else
   size(8);
   format %{ "FMSR     $dst,$src \n\t"
             "FSITOS   $dst, $dst"%}
@@ -9992,19 +7301,11 @@
       __ fmsr($dst$$FloatRegister, $src$$Register);
       __ fsitos($dst$$FloatRegister, $dst$$FloatRegister);
   %}
-#endif
   ins_pipe(fcvtI2F);
 %}
 
 instruct convI2L_reg(iRegL dst, iRegI src) %{
   match(Set dst (ConvI2L src));
-#ifdef AARCH64
-  size(4);
-  format %{ "SXTW   $dst,$src\t! int->long" %}
-  ins_encode %{
-    __ sxtw($dst$$Register, $src$$Register);
-  %}
-#else
   size(8);
   format %{ "MOV    $dst.lo, $src \n\t"
             "ASR    $dst.hi,$src,31\t! int->long" %}
@@ -10012,20 +7313,12 @@
     __ mov($dst$$Register, $src$$Register);
     __ mov($dst$$Register->successor(), AsmOperand($src$$Register, asr, 31));
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
 // Zero-extend convert int to long
 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
   match(Set dst (AndL (ConvI2L src) mask) );
-#ifdef AARCH64
-  size(4);
-  format %{ "mov_w  $dst,$src\t! zero-extend int to long"  %}
-  ins_encode %{
-    __ mov_w($dst$$Register, $src$$Register);
-  %}
-#else
   size(8);
   format %{ "MOV    $dst.lo,$src.lo\t! zero-extend int to long\n\t"
             "MOV    $dst.hi, 0"%}
@@ -10033,20 +7326,12 @@
     __ mov($dst$$Register, $src$$Register);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
 // Zero-extend long
 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
   match(Set dst (AndL src mask) );
-#ifdef AARCH64
-  size(4);
-  format %{ "mov_w  $dst,$src\t! zero-extend long"  %}
-  ins_encode %{
-    __ mov_w($dst$$Register, $src$$Register);
-  %}
-#else
   size(8);
   format %{ "MOV    $dst.lo,$src.lo\t! zero-extend long\n\t"
             "MOV    $dst.hi, 0"%}
@@ -10054,7 +7339,6 @@
     __ mov($dst$$Register, $src$$Register);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
@@ -10089,17 +7373,10 @@
   ins_cost(MEMORY_REF_COST); // FIXME
 
   size(4);
-#ifdef AARCH64
-  format %{ "FMOV_xd  $dst,$src\t! MoveD2L" %}
-  ins_encode %{
-    __ fmov_xd($dst$$Register, $src$$FloatRegister);
-  %}
-#else
   format %{ "FMRRD    $dst,$src\t! MoveD2L" %}
   ins_encode %{
     __ fmrrd($dst$$Register, $dst$$Register->successor(), $src$$FloatRegister);
   %}
-#endif
   ins_pipe(iload_mem); // FIXME
 %}
 
@@ -10109,46 +7386,16 @@
   ins_cost(MEMORY_REF_COST); // FIXME
 
   size(4);
-#ifdef AARCH64
-  format %{ "FMOV_dx $dst,$src\t! MoveL2D" %}
-  ins_encode %{
-    __ fmov_dx($dst$$FloatRegister, $src$$Register);
-  %}
-#else
   format %{ "FMDRR   $dst,$src\t! MoveL2D" %}
   ins_encode %{
     __ fmdrr($dst$$FloatRegister, $src$$Register, $src$$Register->successor());
   %}
-#endif
   ins_pipe(ialu_reg_reg); // FIXME
 %}
 
 //-----------
 // Long to Double conversion
 
-#ifdef AARCH64
-instruct convL2D(regD dst, iRegL src) %{
-  match(Set dst (ConvL2D src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  size(4);
-  format %{ "SCVTF_dx $dst, $src" %}
-  ins_encode %{
-    __ scvtf_dx($dst$$FloatRegister, $src$$Register);
-  %}
-  ins_pipe(fcvtL2D);
-%}
-
-instruct convL2F(regF dst, iRegL src) %{
-  match(Set dst (ConvL2F src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  size(4);
-  format %{ "SCVTF_sx $dst, $src" %}
-  ins_encode %{
-    __ scvtf_sx($dst$$FloatRegister, $src$$Register);
-  %}
-  ins_pipe(fcvtL2F);
-%}
-#else
 // Magic constant, 0x43300000
 instruct loadConI_x43300000(iRegI dst) %{
   effect(DEF dst);
@@ -10194,7 +7441,6 @@
   ins_pipe(faddD_reg_reg);
 %}
 
-#ifndef AARCH64
 // Convert integer in high half of a double register (in the lower half of
 // the double register file) to double
 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
@@ -10206,7 +7452,6 @@
   %}
   ins_pipe(fcvtLHi2D);
 %}
-#endif
 
 // Add float double precision
 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
@@ -10297,26 +7542,17 @@
     addD_regD_regD(dst, tmp3, tmp4);
   %}
 %}
-#endif // !AARCH64
 
 instruct convL2I_reg(iRegI dst, iRegL src) %{
   match(Set dst (ConvL2I src));
   size(4);
-#ifdef AARCH64
-  format %{ "MOV_w  $dst,$src\t! long->int" %}
-  ins_encode %{
-    __ mov_w($dst$$Register, $src$$Register);
-  %}
-#else
   format %{ "MOV    $dst,$src.lo\t! long->int" %}
   ins_encode %{
     __ mov($dst$$Register, $src$$Register);
   %}
-#endif
   ins_pipe(ialu_move_reg_I_to_L);
 %}
 
-#ifndef AARCH64
 // Register Shift Right Immediate
 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
   match(Set dst (ConvL2I (RShiftL src cnt)));
@@ -10331,7 +7567,6 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 
 //----------Control Flow Instructions------------------------------------------
@@ -10410,7 +7645,6 @@
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
 
-#ifndef AARCH64
 instruct testshlI_reg_reg_reg( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, iRegI op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (LShiftI op2 op3)) zero));
   size(4);
@@ -10421,7 +7655,6 @@
   %}
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
-#endif
 
 instruct testshlI_reg_reg_imm( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, immU5 op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (LShiftI op2 op3)) zero));
@@ -10434,7 +7667,6 @@
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
 
-#ifndef AARCH64
 instruct testsarI_reg_reg_reg( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, iRegI op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (RShiftI op2 op3)) zero));
   size(4);
@@ -10445,7 +7677,6 @@
   %}
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
-#endif
 
 instruct testsarI_reg_reg_imm( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, immU5 op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (RShiftI op2 op3)) zero));
@@ -10458,7 +7689,6 @@
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
 
-#ifndef AARCH64
 instruct testshrI_reg_reg_reg( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, iRegI op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (URShiftI op2 op3)) zero));
   size(4);
@@ -10469,7 +7699,6 @@
   %}
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
-#endif
 
 instruct testshrI_reg_reg_imm( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, immU5 op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (URShiftI op2 op3)) zero));
@@ -10493,31 +7722,6 @@
   ins_pipe(ialu_cconly_reg_imm_zero);
 %}
 
-#ifdef AARCH64
-instruct compL_reg_reg(flagsReg xcc, iRegL op1, iRegL op2)
-%{
-  match(Set xcc (CmpL op1 op2));
-  effect( DEF xcc, USE op1, USE op2 );
-
-  size(4);
-  format %{ "CMP     $op1,$op2\t! long" %}
-  ins_encode %{
-    __ cmp($op1$$Register, $op2$$Register);
-  %}
-  ins_pipe(ialu_cconly_reg_reg);
-%}
-
-instruct compUL_iReg(flagsRegU xcc, iRegL op1, iRegL op2) %{
-  match(Set xcc (CmpUL op1 op2));
-
-  size(4);
-  format %{ "CMP     $op1,$op2\t! unsigned long" %}
-  ins_encode %{
-    __ cmp($op1$$Register, $op2$$Register);
-  %}
-  ins_pipe(ialu_cconly_reg_reg);
-%}
-#else
 instruct compL_reg_reg_LTGE(flagsRegL_LTGE xcc, iRegL op1, iRegL op2, iRegL tmp) %{
   match(Set xcc (CmpL op1 op2));
   effect( DEF xcc, USE op1, USE op2, TEMP tmp );
@@ -10545,35 +7749,7 @@
   %}
   ins_pipe(ialu_cconly_reg_reg);
 %}
-#endif
-
-#ifdef AARCH64
-instruct compL_reg_con(flagsReg xcc, iRegL op1, aimmL con) %{
-  match(Set xcc (CmpL op1 con));
-  effect( DEF xcc, USE op1, USE con );
-
-  size(8);
-  format %{ "CMP     $op1,$con\t\t! long"  %}
-  ins_encode %{
-    __ cmp($op1$$Register, $con$$constant);
-  %}
-
-  ins_pipe(ialu_cconly_reg_imm);
-%}
-
-instruct compUL_reg_con(flagsRegU xcc, iRegL op1, aimmL con) %{
-  match(Set xcc (CmpUL op1 con));
-  effect(DEF xcc, USE op1, USE con);
-
-  size(8);
-  format %{ "CMP     $op1,$con\t\t! unsigned long"  %}
-  ins_encode %{
-    __ cmp($op1$$Register, $con$$constant);
-  %}
-
-  ins_pipe(ialu_cconly_reg_imm);
-%}
-#else
+
 instruct compL_reg_reg_EQNE(flagsRegL_EQNE xcc, iRegL op1, iRegL op2) %{
   match(Set xcc (CmpL op1 op2));
   effect( DEF xcc, USE op1, USE op2 );
@@ -10731,7 +7907,6 @@
 
   ins_pipe(ialu_cconly_reg_reg);
 %}
-#endif
 
 /* instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ */
 /*   match(Set xcc (CmpL (AndL op1 op2) zero)); */
@@ -10839,13 +8014,6 @@
   match(Set icc (CmpF src1 src2));
   effect(KILL fcc);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "FCMP_s  $src1,$src2" %}
-  ins_encode %{
-    __ fcmp_s($src1$$FloatRegister, $src2$$FloatRegister);
-  %}
-#else
   size(8);
   format %{ "FCMPs  $src1,$src2\n\t"
             "FMSTAT" %}
@@ -10853,7 +8021,6 @@
     __ fcmps($src1$$FloatRegister, $src2$$FloatRegister);
     __ fmstat();
   %}
-#endif
   ins_pipe(faddF_fcc_reg_reg_zero);
 %}
 
@@ -10861,13 +8028,6 @@
   match(Set icc (CmpF src1 src2));
   effect(KILL fcc);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "FCMP0_s $src1" %}
-  ins_encode %{
-    __ fcmp0_s($src1$$FloatRegister);
-  %}
-#else
   size(8);
   format %{ "FCMPs  $src1,$src2\n\t"
             "FMSTAT" %}
@@ -10875,7 +8035,6 @@
     __ fcmpzs($src1$$FloatRegister);
     __ fmstat();
   %}
-#endif
   ins_pipe(faddF_fcc_reg_reg_zero);
 %}
 
@@ -10883,13 +8042,6 @@
   match(Set icc (CmpD src1 src2));
   effect(KILL fcc);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "FCMP_d $src1,$src2" %}
-  ins_encode %{
-    __ fcmp_d($src1$$FloatRegister, $src2$$FloatRegister);
-  %}
-#else
   size(8);
   format %{ "FCMPd  $src1,$src2 \n\t"
             "FMSTAT" %}
@@ -10897,7 +8049,6 @@
     __ fcmpd($src1$$FloatRegister, $src2$$FloatRegister);
     __ fmstat();
   %}
-#endif
   ins_pipe(faddD_fcc_reg_reg_zero);
 %}
 
@@ -10905,13 +8056,6 @@
   match(Set icc (CmpD src1 src2));
   effect(KILL fcc);
 
-#ifdef AARCH64
-  size(8);
-  format %{ "FCMP0_d $src1" %}
-  ins_encode %{
-    __ fcmp0_d($src1$$FloatRegister);
-  %}
-#else
   size(8);
   format %{ "FCMPZd  $src1,$src2 \n\t"
             "FMSTAT" %}
@@ -10919,87 +8063,9 @@
     __ fcmpzd($src1$$FloatRegister);
     __ fmstat();
   %}
-#endif
   ins_pipe(faddD_fcc_reg_reg_zero);
 %}
 
-#ifdef AARCH64
-// Compare floating, generate -1,0,1
-instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg icc) %{
-  match(Set dst (CmpF3 src1 src2));
-  // effect(KILL fcc); // nobody cares if flagsRegF is killed
-  effect(KILL icc);
-  ins_cost(DEFAULT_COST*3); // FIXME
-  size(12);
-  format %{ "FCMP_s $src1,$src2\n\t"
-            "CSET   $dst, gt\n\t"
-            "CSINV  $dst, $dst, ZR, ge" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    __ fcmp_s($src1$$FloatRegister, $src2$$FloatRegister);
-    __ cset(dst, gt);            // 1 if '>', else 0
-    __ csinv(dst, dst, ZR, ge);  // previous value if '>=', else -1
-  %}
-  ins_pipe( floating_cmp ); // FIXME
-%}
-
-// Compare floating, generate -1,0,1
-instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg icc) %{
-  match(Set dst (CmpD3 src1 src2));
-  // effect(KILL fcc); // nobody cares if flagsRegF is killed
-  effect(KILL icc);
-  ins_cost(DEFAULT_COST*3); // FIXME
-  size(12);
-  format %{ "FCMP_d $src1,$src2\n\t"
-            "CSET   $dst, gt\n\t"
-            "CSINV  $dst, $dst, ZR, ge" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    __ fcmp_d($src1$$FloatRegister, $src2$$FloatRegister);
-    __ cset(dst, gt);            // 1 if '>', else 0
-    __ csinv(dst, dst, ZR, ge);  // previous value if '>=', else -1
-  %}
-  ins_pipe( floating_cmp ); // FIXME
-%}
-
-// Compare floating, generate -1,0,1
-instruct cmpF0_reg(iRegI dst, regF src1, immF0 src2, flagsReg icc) %{
-  match(Set dst (CmpF3 src1 src2));
-  // effect(KILL fcc); // nobody cares if flagsRegF is killed
-  effect(KILL icc);
-  ins_cost(DEFAULT_COST*3); // FIXME
-  size(12);
-  format %{ "FCMP0_s $src1\n\t"
-            "CSET   $dst, gt\n\t"
-            "CSINV  $dst, $dst, ZR, ge" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    __ fcmp0_s($src1$$FloatRegister);
-    __ cset(dst, gt);            // 1 if '>', else 0
-    __ csinv(dst, dst, ZR, ge);  // previous value if '>=', else -1
-  %}
-  ins_pipe( floating_cmp ); // FIXME
-%}
-
-// Compare floating, generate -1,0,1
-instruct cmpD0_reg(iRegI dst, regD src1, immD0 src2, flagsReg icc) %{
-  match(Set dst (CmpD3 src1 src2));
-  // effect(KILL fcc); // nobody cares if flagsRegF is killed
-  effect(KILL icc);
-  ins_cost(DEFAULT_COST*3); // FIXME
-  size(12);
-  format %{ "FCMP0_d $src1\n\t"
-            "CSET   $dst, gt\n\t"
-            "CSINV  $dst, $dst, ZR, ge" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    __ fcmp0_d($src1$$FloatRegister);
-    __ cset(dst, gt);            // 1 if '>', else 0
-    __ csinv(dst, dst, ZR, ge);  // previous value if '>=', else -1
-  %}
-  ins_pipe( floating_cmp ); // FIXME
-%}
-#else
 // Compare floating, generate -1,0,1
 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF fcc) %{
   match(Set dst (CmpF3 src1 src2));
@@ -11076,7 +8142,6 @@
   %}
   ins_pipe( floating_cmp );
 %}
-#endif // !AARCH64
 
 //----------Branches---------------------------------------------------------
 // Jump
@@ -11158,61 +8223,6 @@
 %}
 #endif
 
-#ifdef AARCH64
-instruct cbzI(cmpOp cmp, iRegI op1, immI0 op2, label labl) %{
-  match(If cmp (CmpI op1 op2));
-  effect(USE labl);
-  predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq ||
-            _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne);
-  size(4);
-  ins_cost(BRANCH_COST);
-  format %{ "CB{N}Z $op1, $labl\t! int $cmp" %}
-  ins_encode %{
-    if ($cmp$$cmpcode == eq) {
-      __ cbz_w($op1$$Register, *($labl$$label));
-    } else {
-      __ cbnz_w($op1$$Register, *($labl$$label));
-    }
-  %}
-  ins_pipe(br_cc); // FIXME
-%}
-
-instruct cbzP(cmpOpP cmp, iRegP op1, immP0 op2, label labl) %{
-  match(If cmp (CmpP op1 op2));
-  effect(USE labl);
-  predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq ||
-            _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne);
-  size(4);
-  ins_cost(BRANCH_COST);
-  format %{ "CB{N}Z $op1, $labl\t! ptr $cmp" %}
-  ins_encode %{
-    if ($cmp$$cmpcode == eq) {
-      __ cbz($op1$$Register, *($labl$$label));
-    } else {
-      __ cbnz($op1$$Register, *($labl$$label));
-    }
-  %}
-  ins_pipe(br_cc); // FIXME
-%}
-
-instruct cbzL(cmpOpL cmp, iRegL op1, immL0 op2, label labl) %{
-  match(If cmp (CmpL op1 op2));
-  effect(USE labl);
-  predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq ||
-            _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne);
-  size(4);
-  ins_cost(BRANCH_COST);
-  format %{ "CB{N}Z $op1, $labl\t! long $cmp" %}
-  ins_encode %{
-    if ($cmp$$cmpcode == eq) {
-      __ cbz($op1$$Register, *($labl$$label));
-    } else {
-      __ cbnz($op1$$Register, *($labl$$label));
-    }
-  %}
-  ins_pipe(br_cc); // FIXME
-%}
-#endif
 
 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
   match(If cmp icc);
@@ -11240,7 +8250,6 @@
   ins_pipe(br_cc);
 %}
 
-#ifndef AARCH64
 instruct branchConL_LTGE(cmpOpL cmp, flagsRegL_LTGE xcc, label labl) %{
   match(If cmp xcc);
   effect(USE labl);
@@ -11324,7 +8333,6 @@
   %}
   ins_pipe(br_cc);
 %}
-#endif
 
 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
   match(CountedLoopEnd cmp icc);
@@ -11372,26 +8380,6 @@
 
 // Manifest a CmpL3 result in an integer register.  Very painful.
 // This is the test to avoid.
-#ifdef AARCH64
-instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr) %{
-  match(Set dst (CmpL3 src1 src2));
-  // effect(KILL fcc); // nobody cares if flagsRegF is killed
-  effect(KILL ccr);
-  ins_cost(DEFAULT_COST*3); // FIXME
-  size(12);
-  format %{ "CMP    $src1,$src2\n\t"
-            "CSET   $dst, gt\n\t"
-            "CSINV  $dst, $dst, ZR, ge" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    __ cmp($src1$$Register, $src2$$Register);
-    __ cset(dst, gt);            // 1 if '>', else 0
-    __ csinv(dst, dst, ZR, ge);  // previous value if '>=', else -1
-  %}
-  ins_pipe( ialu_cconly_reg_reg ); // FIXME
-%}
-// TODO cmpL3_reg_imm
-#else
 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
   match(Set dst (CmpL3 src1 src2) );
   effect( KILL ccr );
@@ -11419,9 +8407,7 @@
   %}
   ins_pipe(cmpL_reg);
 %}
-#endif
-
-#ifndef AARCH64
+
 // Conditional move
 instruct cmovLL_reg_LTGE(cmpOpL cmp, flagsRegL_LTGE xcc, iRegL dst, iRegL src) %{
   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
@@ -11509,9 +8495,7 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif // !AARCH64
-
-#ifndef AARCH64
+
 instruct cmovIL_reg_LTGE(cmpOpL cmp, flagsRegL_LTGE xcc, iRegI dst, iRegI src) %{
   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
   predicate(_kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
@@ -11550,9 +8534,7 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif // !AARCH64
-
-#ifndef AARCH64
+
 instruct cmovIL_imm_LTGE(cmpOpL cmp, flagsRegL_LTGE xcc, iRegI dst, immI16 src) %{
   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
   predicate(_kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
@@ -11738,25 +8720,9 @@
   %}
   ins_pipe(int_conditional_float_move);
 %}
-#endif // !AARCH64
 
 // ============================================================================
 // Safepoint Instruction
-#ifdef AARCH64
-instruct safePoint_poll(iRegP poll, flagsReg icc, RtempRegP tmp) %{
-  match(SafePoint poll);
-  // The handler stub kills Rtemp
-  effect(USE poll, KILL tmp, KILL icc);
-
-  size(4);
-  format %{ "LDR   ZR,[$poll]\t! Safepoint: poll for GC" %}
-  ins_encode %{
-    __ relocate(relocInfo::poll_type);
-    __ ldr(ZR, Address($poll$$Register));
-  %}
-  ins_pipe(loadPollP);
-%}
-#else
 // rather than KILL R12, it would be better to use any reg as
 // TEMP. Can't do that at this point because it crashes the compiler
 instruct safePoint_poll(iRegP poll, R12RegI tmp, flagsReg icc) %{
@@ -11771,7 +8737,6 @@
   %}
   ins_pipe(loadPollP);
 %}
-#endif
 
 
 // ============================================================================
@@ -11820,13 +8785,8 @@
   effect(USE meth);
   ins_cost(CALL_COST);
   format %{ "CALL,runtime" %}
-#ifdef AARCH64
-  ins_encode( save_last_PC, Java_To_Runtime( meth ),
-              call_epilog );
-#else
   ins_encode( Java_To_Runtime( meth ),
               call_epilog );
-#endif
   ins_pipe(simple_call);
 %}
 
@@ -11952,11 +8912,7 @@
   // Use the following format syntax
   format %{ "ShouldNotReachHere" %}
   ins_encode %{
-#ifdef AARCH64
-    __ dpcs1(0xdead);
-#else
     __ udf(0xdead);
-#endif
   %}
   ins_pipe(tail_call);
 %}
@@ -11986,49 +8942,21 @@
 // ============================================================================
 // inlined locking and unlocking
 
-#ifdef AARCH64
-instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, iRegP scratch, iRegP scratch3 )
-#else
 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, iRegP scratch )
-#endif
 %{
   match(Set pcc (FastLock object box));
 
-#ifdef AARCH64
-  effect(TEMP scratch, TEMP scratch2, TEMP scratch3);
-#else
   effect(TEMP scratch, TEMP scratch2);
-#endif
   ins_cost(100);
 
-#ifdef AARCH64
-  format %{ "FASTLOCK  $object, $box; KILL $scratch, $scratch2, $scratch3" %}
-  ins_encode %{
-    __ fast_lock($object$$Register, $box$$Register, $scratch$$Register, $scratch2$$Register, $scratch3$$Register);
-  %}
-#else
   format %{ "FASTLOCK  $object, $box; KILL $scratch, $scratch2" %}
   ins_encode %{
     __ fast_lock($object$$Register, $box$$Register, $scratch$$Register, $scratch2$$Register);
   %}
-#endif
   ins_pipe(long_memory_op);
 %}
 
 
-#ifdef AARCH64
-instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, iRegP scratch, iRegP scratch3 ) %{
-  match(Set pcc (FastUnlock object box));
-  effect(TEMP scratch, TEMP scratch2, TEMP scratch3);
-  ins_cost(100);
-
-  format %{ "FASTUNLOCK  $object, $box; KILL $scratch, $scratch2, $scratch3" %}
-  ins_encode %{
-    __ fast_unlock($object$$Register, $box$$Register, $scratch$$Register, $scratch2$$Register, $scratch3$$Register);
-  %}
-  ins_pipe(long_memory_op);
-%}
-#else
 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, iRegP scratch ) %{
   match(Set pcc (FastUnlock object box));
   effect(TEMP scratch, TEMP scratch2);
@@ -12040,48 +8968,7 @@
   %}
   ins_pipe(long_memory_op);
 %}
-#endif
-
-#ifdef AARCH64
-// TODO: add version that takes immI cnt?
-instruct clear_array(iRegX cnt, iRegP base, iRegP ptr, iRegX temp, Universe dummy, flagsReg cpsr) %{
-  match(Set dummy (ClearArray cnt base));
-  effect(TEMP temp, TEMP ptr, KILL cpsr);
-  ins_cost(300);
-  format %{
-      "        MOV    $temp,$cnt\n"
-      "        ADD    $ptr,$base,$cnt\n"
-      "        SUBS   $temp,$temp,16\t! Count down dword pair in bytes\n"
-      "        B.lt   done16\n"
-      "loop:   STP    ZR,ZR,[$ptr,-16]!\n"
-      "        SUBS   $temp,$temp,16\t! Count down dword pair in bytes\n"
-      "        B.ge   loop\t! Clearing loop\n"
-      "done16: ADDS   $temp,$temp,8\t! Room for 1 more long?\n"
-      "        B.lt   done\n"
-      "        STR    ZR,[$base+$temp]\n"
-      "done:"
-  %}
-  ins_encode %{
-    // TODO: preload?
-    __ mov($temp$$Register, $cnt$$Register);
-    __ add($ptr$$Register, $base$$Register, $cnt$$Register);
-    Label loop, done, done16;
-    __ subs($temp$$Register, $temp$$Register, 16);
-    __ b(done16, lt);
-    __ bind(loop);
-    __ stp(ZR, ZR, Address($ptr$$Register, -16, pre_indexed));
-    __ subs($temp$$Register, $temp$$Register, 16);
-    __ b(loop, ge);
-    __ bind(done16);
-    __ adds($temp$$Register, $temp$$Register, 8);
-    __ b(done, lt);
-    // $temp should be 0 here
-    __ str(ZR, Address($base$$Register, $temp$$Register));
-    __ bind(done);
-  %}
-  ins_pipe(long_memory_op);
-%}
-#else
+
 // Count and Base registers are fixed because the allocator cannot
 // kill unknown registers.  The encodings are generic.
 instruct clear_array(iRegX cnt, iRegP base, iRegI temp, iRegX zero, Universe dummy, flagsReg cpsr) %{
@@ -12104,7 +8991,6 @@
   %}
   ins_pipe(long_memory_op);
 %}
-#endif
 
 #ifdef XXX
 // FIXME: Why R0/R1/R2/R3?
@@ -12159,17 +9045,6 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifdef AARCH64
-instruct countLeadingZerosL(iRegI dst, iRegL src) %{
-  match(Set dst (CountLeadingZerosL src));
-  size(4);
-  format %{ "CLZ $dst,$src" %}
-  ins_encode %{
-    __ clz($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-#else
 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegI tmp, flagsReg ccr) %{
   match(Set dst (CountLeadingZerosL src));
   effect(TEMP tmp, TEMP dst, KILL ccr);
@@ -12186,7 +9061,6 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif
 
 instruct countTrailingZerosI(iRegI dst, iRegI src, iRegI tmp) %{
   match(Set dst (CountTrailingZerosI src));
@@ -12201,20 +9075,6 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifdef AARCH64
-instruct countTrailingZerosL(iRegI dst, iRegL src, iRegL tmp) %{
-  match(Set dst (CountTrailingZerosL src));
-  effect(TEMP tmp);
-  size(8);
-  format %{ "RBIT $tmp, $src\n\t"
-            "CLZ  $dst,$tmp" %}
-  ins_encode %{
-    __ rbit($tmp$$Register, $src$$Register);
-    __ clz($dst$$Register, $tmp$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-#else
 instruct countTrailingZerosL(iRegI dst, iRegL src, iRegI tmp, flagsReg ccr) %{
   match(Set dst (CountTrailingZerosL src));
   effect(TEMP tmp, TEMP dst, KILL ccr);
@@ -12235,37 +9095,10 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif
 
 
 //---------- Population Count Instructions -------------------------------------
 
-#ifdef AARCH64
-instruct popCountI(iRegI dst, iRegI src, regD_low tmp) %{
-  predicate(UsePopCountInstruction);
-  match(Set dst (PopCountI src));
-  effect(TEMP tmp);
-  size(20);
-
-  format %{ "MOV_W      $dst,$src\n\t"
-            "FMOV_dx    $tmp,$dst\n\t"
-            "VCNT       $tmp.8B,$tmp.8B\n\t"
-            "ADDV       $tmp.B,$tmp.8B\n\t"
-            "FMRS       $dst,$tmp" %}
-
-  ins_encode %{
-    __ mov_w($dst$$Register, $src$$Register);
-    __ fmov_dx($tmp$$FloatRegister, $dst$$Register);
-    int quad = 0;
-    int cnt_size = 0; // VELEM_SIZE_8
-    __ vcnt($tmp$$FloatRegister, $tmp$$FloatRegister, quad, cnt_size);
-    int add_size = 0; // VELEM_SIZE_8
-    __ addv($tmp$$FloatRegister, $tmp$$FloatRegister, quad, add_size);
-    __ fmrs($dst$$Register, $tmp$$FloatRegister);
-  %}
-  ins_pipe(ialu_reg); // FIXME
-%}
-#else
 instruct popCountI(iRegI dst, iRegI src, regD_low tmp) %{
   predicate(UsePopCountInstruction);
   match(Set dst (PopCountI src));
@@ -12287,32 +9120,7 @@
   %}
   ins_pipe(ialu_reg); // FIXME
 %}
-#endif
-
-#ifdef AARCH64
-instruct popCountL(iRegI dst, iRegL src, regD tmp) %{
-  predicate(UsePopCountInstruction);
-  match(Set dst (PopCountL src));
-  effect(TEMP tmp);
-  size(16);
-
-  format %{ "FMOV_dx    $tmp,$src\n\t"
-            "VCNT       $tmp.8B,$tmp.8B\n\t"
-            "ADDV       $tmp.B,$tmp.8B\n\t"
-            "FMOV_ws    $dst,$tmp" %}
-
-  ins_encode %{
-    __ fmov_dx($tmp$$FloatRegister, $src$$Register);
-    int quad = 0;
-    int cnt_size = 0;
-    __ vcnt($tmp$$FloatRegister, $tmp$$FloatRegister, quad, cnt_size);
-    int add_size = 0;
-    __ addv($tmp$$FloatRegister, $tmp$$FloatRegister, quad, add_size);
-    __ fmov_ws($dst$$Register, $tmp$$FloatRegister);
-  %}
-  ins_pipe(ialu_reg); // FIXME
-%}
-#else
+
 // Note: Long.bitCount(long) returns an int.
 instruct popCountL(iRegI dst, iRegL src, regD_low tmp) %{
   predicate(UsePopCountInstruction);
@@ -12338,7 +9146,6 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif
 
 
 // ============================================================================
@@ -12350,26 +9157,13 @@
   size(4);
   format %{ "REV32 $dst,$src" %}
   ins_encode %{
-#ifdef AARCH64
-    __ rev_w($dst$$Register, $src$$Register);
-    // high 32 bits zeroed, not sign extended
-#else
     __ rev($dst$$Register, $src$$Register);
-#endif
   %}
   ins_pipe( iload_mem ); // FIXME
 %}
 
 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
   match(Set dst (ReverseBytesL src));
-#ifdef AARCH64
-//size(4);
-  format %{ "REV $dst,$src"  %}
-  ins_encode %{
-    __ rev($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-#else
   effect(TEMP dst);
   size(8);
   format %{ "REV $dst.lo,$src.lo\n\t"
@@ -12379,45 +9173,25 @@
     __ rev($dst$$Register->successor(), $src$$Register);
   %}
   ins_pipe( iload_mem ); // FIXME
-#endif
 %}
 
 instruct bytes_reverse_unsigned_short(iRegI dst, iRegI src) %{
   match(Set dst (ReverseBytesUS src));
-#ifdef AARCH64
-  size(4);
-  format %{ "REV16_W $dst,$src" %}
-  ins_encode %{
-    __ rev16_w($dst$$Register, $src$$Register);
-    // high 32 bits zeroed
-  %}
-#else
   size(4);
   format %{ "REV16 $dst,$src" %}
   ins_encode %{
     __ rev16($dst$$Register, $src$$Register);
   %}
-#endif
   ins_pipe( iload_mem ); // FIXME
 %}
 
 instruct bytes_reverse_short(iRegI dst, iRegI src) %{
   match(Set dst (ReverseBytesS src));
-#ifdef AARCH64
-  size(8);
-  format %{ "REV16_W $dst,$src\n\t"
-            "SIGN_EXT16 $dst" %}
-  ins_encode %{
-    __ rev16_w($dst$$Register, $src$$Register);
-    __ sign_extend($dst$$Register, $dst$$Register, 16);
-  %}
-#else
   size(4);
   format %{ "REVSH $dst,$src" %}
   ins_encode %{
     __ revsh($dst$$Register, $src$$Register);
   %}
-#endif
   ins_pipe( iload_mem ); // FIXME
 %}
 
@@ -12476,7 +9250,6 @@
   ins_pipe(fstoreD_mem_reg); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar to packed byte values in Double register
 instruct Repl8B_reg(vecD dst, iRegI src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 8);
@@ -12498,7 +9271,6 @@
   %}
   ins_pipe(ialu_reg); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar to packed byte values in Double register
 instruct Repl8B_reg_simd(vecD dst, iRegI src) %{
@@ -12530,7 +9302,6 @@
   ins_pipe(ialu_reg); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar constant to packed byte values in Double register
 instruct Repl8B_immI(vecD dst, immI src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 8);
@@ -12544,7 +9315,6 @@
   ins_encode( LdReplImmI(src, dst, tmp, (4), (1)) );
   ins_pipe(loadConFD); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar constant to packed byte values in Double register
 // TODO: support negative constants with MVNI?
@@ -12577,7 +9347,6 @@
   ins_pipe(loadConFD); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar to packed short/char values into Double register
 instruct Repl4S_reg(vecD dst, iRegI src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 4);
@@ -12597,7 +9366,6 @@
   %}
   ins_pipe(ialu_reg); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar to packed byte values in Double register
 instruct Repl4S_reg_simd(vecD dst, iRegI src) %{
@@ -12630,7 +9398,6 @@
 %}
 
 
-#ifndef AARCH64
 // Replicate scalar constant to packed short/char values in Double register
 instruct Repl4S_immI(vecD dst, immI src, iRegP tmp) %{
   predicate(n->as_Vector()->length() == 4);
@@ -12644,7 +9411,6 @@
   ins_encode( LdReplImmI(src, dst, tmp, (2), (2)) );
   ins_pipe(loadConFD); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar constant to packed byte values in Double register
 instruct Repl4S_immU8(vecD dst, immU8 src) %{
@@ -12676,7 +9442,6 @@
   ins_pipe(loadConFD); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar to packed int values in Double register
 instruct Repl2I_reg(vecD dst, iRegI src) %{
   predicate(n->as_Vector()->length() == 2);
@@ -12707,7 +9472,6 @@
   %}
   ins_pipe(ialu_reg); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar to packed int values in Double register
 instruct Repl2I_reg_simd(vecD dst, iRegI src) %{
@@ -12740,7 +9504,6 @@
 %}
 
 
-#ifndef AARCH64
 // Replicate scalar zero constant to packed int values in Double register
 instruct Repl2I_immI(vecD dst, immI src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 2);
@@ -12754,7 +9517,6 @@
   ins_encode( LdReplImmI(src, dst, tmp, (1), (4)) );
   ins_pipe(loadConFD); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar constant to packed byte values in Double register
 instruct Repl2I_immU8(vecD dst, immU8 src) %{
@@ -12786,23 +9548,6 @@
   ins_pipe(loadConFD); // FIXME
 %}
 
-#ifdef AARCH64
-// Replicate scalar to packed byte values in Double register pair
-instruct Repl2L_reg(vecX dst, iRegL src) %{
-  predicate(n->as_Vector()->length() == 2);
-  match(Set dst (ReplicateL src));
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "VDUP.2D $dst.Q,$src\t" %}
-  ins_encode %{
-    bool quad = true;
-    __ vdupI($dst$$FloatRegister, $src$$Register,
-             MacroAssembler::VELEM_SIZE_64, quad);
-  %}
-  ins_pipe(ialu_reg); // FIXME
-%}
-#else /* !AARCH64 */
 // Replicate scalar to packed byte values in Double register pair
 instruct Repl2L_reg(vecX dst, iRegL src) %{
   predicate(n->as_Vector()->length() == 2);
@@ -12847,7 +9592,6 @@
     Repl2F_regI(dst,tmp);
   %}
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar to packed float values in Double register
 instruct Repl2F_reg_simd(vecD dst, regF src) %{
@@ -12864,7 +9608,6 @@
   ins_pipe(ialu_reg); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar to packed float values in Double register pair
 instruct Repl4F_reg(vecX dst, regF src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 4);
@@ -12884,7 +9627,6 @@
   %}
   ins_pipe(ialu_reg); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar to packed float values in Double register pair
 instruct Repl4F_reg_simd(vecX dst, regF src) %{
@@ -12901,7 +9643,6 @@
   ins_pipe(ialu_reg); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar zero constant to packed float values in Double register
 instruct Repl2F_immI(vecD dst, immF src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 2);
@@ -12915,22 +9656,9 @@
   ins_encode( LdReplImmF(src, dst, tmp) );
   ins_pipe(loadConFD); // FIXME
 %}
-#endif /* !AAARCH64 */
 
 // Replicate scalar to packed double float values in Double register pair
 instruct Repl2D_reg(vecX dst, regD src) %{
-#ifdef AARCH64
-  predicate(n->as_Vector()->length() == 2 && VM_Version::has_simd());
-  match(Set dst (ReplicateD src));
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "VDUP     $dst.2D,$src\t" %}
-  ins_encode %{
-    bool quad = true;
-    __ vdupD($dst$$FloatRegister, $src$$FloatRegister, quad);
-  %}
-#else
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (ReplicateD src));
   size(4*2);
@@ -12945,7 +9673,6 @@
     FloatRegister dstb = dsta->successor()->successor();
     __ fcpyd(dstb, src);
   %}
-#endif
   ins_pipe(ialu_reg); // FIXME
 %}
 
@@ -13062,7 +9789,6 @@
   ins_pipe( faddD_reg_reg ); // FIXME
 %}
 
-#ifndef AARCH64
 instruct vadd2F_reg_vfp(vecD dst, vecD src1, vecD src2) %{
   predicate(n->as_Vector()->length() == 2 && !VM_Version::simd_math_is_compliant());
   match(Set dst (AddVF src1 src2));
@@ -13080,7 +9806,6 @@
 
   ins_pipe(faddF_reg_reg); // FIXME
 %}
-#endif
 
 instruct vadd4F_reg_simd(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4 && VM_Version::simd_math_is_compliant());
@@ -13095,20 +9820,6 @@
   ins_pipe( faddD_reg_reg ); // FIXME
 %}
 
-#ifdef AARCH64
-instruct vadd2D_reg_simd(vecX dst, vecX src1, vecX src2) %{
-  predicate(n->as_Vector()->length() == 2 && VM_Version::simd_math_is_compliant());
-  match(Set dst (AddVD src1 src2));
-  size(4);
-  format %{ "VADD.F64 $dst.Q,$src1.Q,$src2.Q\t! add packed2D" %}
-  ins_encode %{
-    bool quad = true;
-    __ vaddF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F64, quad);
-  %}
-  ins_pipe( faddD_reg_reg ); // FIXME
-%}
-#else
 instruct vadd4F_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4 && !VM_Version::simd_math_is_compliant());
   match(Set dst (AddVF src1 src2));
@@ -13164,7 +9875,6 @@
 
   ins_pipe(faddF_reg_reg); // FIXME
 %}
-#endif
 
 
 // Bytes vector sub
@@ -13276,7 +9986,6 @@
   ins_pipe( faddF_reg_reg ); // FIXME
 %}
 
-#ifndef AARCH64
 instruct vsub2F_reg_vfp(vecD dst, vecD src1, vecD src2) %{
   predicate(n->as_Vector()->length() == 2 && !VM_Version::simd_math_is_compliant());
   match(Set dst (SubVF src1 src2));
@@ -13299,7 +10008,6 @@
 
   ins_pipe(faddF_reg_reg); // FIXME
 %}
-#endif
 
 
 instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{
@@ -13315,20 +10023,6 @@
   ins_pipe( faddF_reg_reg ); // FIXME
 %}
 
-#ifdef AARCH64
-instruct vsub2D_reg_simd(vecX dst, vecX src1, vecX src2) %{
-  predicate(n->as_Vector()->length() == 2 && VM_Version::simd_math_is_compliant());
-  match(Set dst (SubVD src1 src2));
-  size(4);
-  format %{ "VSUB.F64 $dst.Q,$src1.Q,$src2.Q\t! add packed2D" %}
-  ins_encode %{
-    bool quad = true;
-    __ vsubF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F64, quad);
-  %}
-  ins_pipe( faddD_reg_reg ); // FIXME
-%}
-#else
 instruct vsub4F_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4 && !VM_Version::simd_math_is_compliant());
   match(Set dst (SubVF src1 src2));
@@ -13384,7 +10078,6 @@
 
   ins_pipe(faddF_reg_reg); // FIXME
 %}
-#endif
 
 // Shorts/Chars vector mul
 instruct vmul4S_reg(vecD dst, vecD src1, vecD src2) %{
@@ -13449,7 +10142,6 @@
   ins_pipe( fmulF_reg_reg ); // FIXME
 %}
 
-#ifndef AARCH64
 instruct vmul2F_reg_vfp(vecD dst, vecD src1, vecD src2) %{
   predicate(n->as_Vector()->length() == 2 && !VM_Version::simd_math_is_compliant());
   match(Set dst (MulVF src1 src2));
@@ -13467,7 +10159,6 @@
 
   ins_pipe(fmulF_reg_reg); // FIXME
 %}
-#endif
 
 instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4 && VM_Version::simd_math_is_compliant());
@@ -13481,7 +10172,6 @@
   ins_pipe( fmulF_reg_reg ); // FIXME
 %}
 
-#ifndef AARCH64
 instruct vmul4F_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4 && !VM_Version::simd_math_is_compliant());
   match(Set dst (MulVF src1 src2));
@@ -13514,25 +10204,7 @@
 
   ins_pipe(fmulF_reg_reg); // FIXME
 %}
-#endif
-
-#ifdef AARCH64
-instruct vmul2D_reg(vecX dst, vecX src1, vecX src2) %{
-  predicate(n->as_Vector()->length() == 2 && VM_Version::has_simd());
-  match(Set dst (MulVD src1 src2));
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "FMUL.2D $dst,$src1,$src2\t! double[2]" %}
-  ins_encode %{
-    int quad = 1;
-    __ vmulF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F64, quad);
-  %}
-
-  ins_pipe(fdivF_reg_reg); // FIXME
-%}
-#else
+
 instruct vmul2D_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (MulVD src1 src2));
@@ -13554,26 +10226,12 @@
 
   ins_pipe(fmulD_reg_reg); // FIXME
 %}
-#endif
 
 
 // Floats vector div
 instruct vdiv2F_reg_vfp(vecD dst, vecD src1, vecD src2) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (DivVF src1 src2));
-#ifdef AARCH64
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "FDIV.2S $dst,$src1,$src2\t! float[2]" %}
-  ins_encode %{
-    int quad = 0;
-    __ vdivF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F32, quad);
-  %}
-
-  ins_pipe(fdivF_reg_reg); // FIXME
-#else
   size(4*2);
   ins_cost(DEFAULT_COST*2); // FIXME
 
@@ -13587,25 +10245,11 @@
   %}
 
   ins_pipe(fdivF_reg_reg); // FIXME
-#endif
 %}
 
 instruct vdiv4F_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4);
   match(Set dst (DivVF src1 src2));
-#ifdef AARCH64
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "FDIV.4S $dst,$src1,$src2\t! float[4]" %}
-  ins_encode %{
-    int quad = 1;
-    __ vdivF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F32, quad);
-  %}
-
-  ins_pipe(fdivF_reg_reg); // FIXME
-#else
   size(4*4);
   ins_cost(DEFAULT_COST*4); // FIXME
 
@@ -13634,26 +10278,8 @@
   %}
 
   ins_pipe(fdivF_reg_reg); // FIXME
-#endif
-%}
-
-#ifdef AARCH64
-instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{
-  predicate(n->as_Vector()->length() == 2 && VM_Version::has_simd());
-  match(Set dst (DivVD src1 src2));
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "FDIV.2D $dst,$src1,$src2\t! double[2]" %}
-  ins_encode %{
-    int quad = 1;
-    __ vdivF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F64, quad);
-  %}
-
-  ins_pipe(fdivF_reg_reg); // FIXME
-%}
-#else
+%}
+
 instruct vdiv2D_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (DivVD src1 src2));
@@ -13675,7 +10301,6 @@
 
   ins_pipe(fdivD_reg_reg); // FIXME
 %}
-#endif
 
 // --------------------------------- NEG --------------------------------------