OpenJDK / portola / portola
changeset 48188:cd85c117a649
8192825: PPC64: Missing null check in C1 inline cache check
Reviewed-by: goetz
author | mdoerr |
---|---|
date | Fri, 01 Dec 2017 17:10:33 +0100 |
parents | c722887b75a2 |
children | acffbbe79871 |
files | src/hotspot/cpu/ppc/c1_MacroAssembler_ppc.cpp |
diffstat | 1 files changed, 9 insertions(+), 4 deletions(-) [+] |
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--- a/src/hotspot/cpu/ppc/c1_MacroAssembler_ppc.cpp Fri Dec 01 17:09:43 2017 +0100 +++ b/src/hotspot/cpu/ppc/c1_MacroAssembler_ppc.cpp Fri Dec 01 17:10:33 2017 +0100 @@ -41,20 +41,25 @@ void C1_MacroAssembler::inline_cache_check(Register receiver, Register iCache) { const Register temp_reg = R12_scratch2; + Label Lmiss; + verify_oop(receiver); + MacroAssembler::null_check(receiver, oopDesc::klass_offset_in_bytes(), &Lmiss); load_klass(temp_reg, receiver); - if (TrapBasedICMissChecks) { + + if (TrapBasedICMissChecks && TrapBasedNullChecks) { trap_ic_miss_check(temp_reg, iCache); } else { - Label L; + Label Lok; cmpd(CCR0, temp_reg, iCache); - beq(CCR0, L); + beq(CCR0, Lok); + bind(Lmiss); //load_const_optimized(temp_reg, SharedRuntime::get_ic_miss_stub(), R0); calculate_address_from_global_toc(temp_reg, SharedRuntime::get_ic_miss_stub(), true, true, false); mtctr(temp_reg); bctr(); align(32, 12); - bind(L); + bind(Lok); } }